//                                                                             
// File:       ./chn1_table_map.vrh                                            
// Creator:    shung                                                           
// Time:       Monday Apr 23, 2012 [6:25:37 pm]                                
//                                                                             
// Path:       /trees/shung/shung-dev/chips/peregrine/1.0/dv/soc/src/ave/regs/blueprint
// Arguments:  /cad/denali/blueprint/3.7.4//Linux/blueprint -odir . -codegen   
//             ath_vrh.codegen -ath_vrh -Wdesc -I                              
//             /trees/shung/shung-dev/chips/peregrine/1.0/blueprint/sysconfig  
//             chn1_table_map.rdl                                              
//                                                                             
// Sources:    /trees/shung/shung-dev/chips/peregrine/1.0/ip/athr/wifi/rtl/mac/rtl/dev/bb/blueprint/chn1_table_map.rdl
//             /trees/shung/shung-dev/chips/peregrine/1.0/env/blueprint/ath_vrh.pm
//             /cad/local/lib/perl/Pinfo.pm                                    
//                                                                             
// Blueprint:   3.7.4 (Tue Jun 23 00:17:01 PDT 2009)                           
// Machine:    vnc2                                                            
// OS:         Linux 2.4.21-40.ELsmp                                           
// Description:                                                                
//                                                                             
// No Description Provided                                                     
/*
 * Copyright (c) 2012-14 Qualcomm Atheros, Inc.
 * All Rights Reserved.
 * Qualcomm Atheros Confidential and Proprietary.
 * $ATH_LICENSE_TARGET_C$
 */


#ifndef _CHN1_TABLE_MAP_H_
#define _CHN1_TABLE_MAP_H_
// 0x0080 (BB_PAPRD_POWER_AT_AM2AM_CAL_B1)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_4_B1_MSB 23
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_4_B1_LSB 18
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_4_B1_MASK 0x00fc0000
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_4_B1_GET(x) (((x) & BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_4_B1_MASK) >> BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_4_B1_LSB)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_4_B1_SET(x) (((0 | (x)) << BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_4_B1_LSB) & BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_4_B1_MASK)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_4_B1_RESET 0
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_3_B1_MSB 17
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_3_B1_LSB 12
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_3_B1_MASK 0x0003f000
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_3_B1_GET(x) (((x) & BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_3_B1_MASK) >> BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_3_B1_LSB)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_3_B1_SET(x) (((0 | (x)) << BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_3_B1_LSB) & BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_3_B1_MASK)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_3_B1_RESET 0
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_2_B1_MSB 11
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_2_B1_LSB 6
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_2_B1_MASK 0x00000fc0
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_2_B1_GET(x) (((x) & BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_2_B1_MASK) >> BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_2_B1_LSB)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_2_B1_SET(x) (((0 | (x)) << BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_2_B1_LSB) & BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_2_B1_MASK)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_2_B1_RESET 0
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_1_B1_MSB 5
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_1_B1_LSB 0
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_1_B1_MASK 0x0000003f
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_1_B1_GET(x) (((x) & BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_1_B1_MASK) >> BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_1_B1_LSB)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_1_B1_SET(x) (((0 | (x)) << BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_1_B1_LSB) & BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_1_B1_MASK)
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_PAPRD_POWER_AT_AM2AM_CAL_1_B1_RESET 0
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_ADDRESS                       0x0080
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_HW_MASK                       0x00ffffff
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_SW_MASK                       0x00ffffff
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_HW_WRITE_MASK                 0x00000000
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_SW_WRITE_MASK                 0x00ffffff
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_RSTMASK                       0xff000000
#define BB_PAPRD_POWER_AT_AM2AM_CAL_B1_RESET                         0x00000000

// 0x0084 (BB_PAPRD_VALID_OBDB_B1)
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_4_B1_MSB             29
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_4_B1_LSB             24
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_4_B1_MASK            0x3f000000
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_4_B1_GET(x)          (((x) & BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_4_B1_MASK) >> BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_4_B1_LSB)
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_4_B1_SET(x)          (((0 | (x)) << BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_4_B1_LSB) & BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_4_B1_MASK)
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_4_B1_RESET           63
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_3_B1_MSB             23
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_3_B1_LSB             18
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_3_B1_MASK            0x00fc0000
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_3_B1_GET(x)          (((x) & BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_3_B1_MASK) >> BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_3_B1_LSB)
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_3_B1_SET(x)          (((0 | (x)) << BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_3_B1_LSB) & BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_3_B1_MASK)
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_3_B1_RESET           63
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_2_B1_MSB             17
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_2_B1_LSB             12
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_2_B1_MASK            0x0003f000
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_2_B1_GET(x)          (((x) & BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_2_B1_MASK) >> BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_2_B1_LSB)
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_2_B1_SET(x)          (((0 | (x)) << BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_2_B1_LSB) & BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_2_B1_MASK)
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_2_B1_RESET           63
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_1_B1_MSB             11
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_1_B1_LSB             6
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_1_B1_MASK            0x00000fc0
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_1_B1_GET(x)          (((x) & BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_1_B1_MASK) >> BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_1_B1_LSB)
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_1_B1_SET(x)          (((0 | (x)) << BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_1_B1_LSB) & BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_1_B1_MASK)
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_1_B1_RESET           63
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_0_B1_MSB             5
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_0_B1_LSB             0
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_0_B1_MASK            0x0000003f
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_0_B1_GET(x)          (((x) & BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_0_B1_MASK) >> BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_0_B1_LSB)
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_0_B1_SET(x)          (((0 | (x)) << BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_0_B1_LSB) & BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_0_B1_MASK)
#define BB_PAPRD_VALID_OBDB_B1_PAPRD_VALID_OBDB_0_B1_RESET           63
#define BB_PAPRD_VALID_OBDB_B1_ADDRESS                               0x0084
#define BB_PAPRD_VALID_OBDB_B1_HW_MASK                               0x3fffffff
#define BB_PAPRD_VALID_OBDB_B1_SW_MASK                               0x3fffffff
#define BB_PAPRD_VALID_OBDB_B1_HW_WRITE_MASK                         0x00000000
#define BB_PAPRD_VALID_OBDB_B1_SW_WRITE_MASK                         0x3fffffff
#define BB_PAPRD_VALID_OBDB_B1_RSTMASK                               0xffffffff
#define BB_PAPRD_VALID_OBDB_B1_RESET                                 0x3fffffff

// 0x0100 (BB_CHN1_TABLES_DUMMY_2)
#define BB_CHN1_TABLES_DUMMY_2_DUMMY2_MSB                            31
#define BB_CHN1_TABLES_DUMMY_2_DUMMY2_LSB                            0
#define BB_CHN1_TABLES_DUMMY_2_DUMMY2_MASK                           0xffffffff
#define BB_CHN1_TABLES_DUMMY_2_DUMMY2_GET(x)                         (((x) & BB_CHN1_TABLES_DUMMY_2_DUMMY2_MASK) >> BB_CHN1_TABLES_DUMMY_2_DUMMY2_LSB)
#define BB_CHN1_TABLES_DUMMY_2_DUMMY2_SET(x)                         (((0 | (x)) << BB_CHN1_TABLES_DUMMY_2_DUMMY2_LSB) & BB_CHN1_TABLES_DUMMY_2_DUMMY2_MASK)
#define BB_CHN1_TABLES_DUMMY_2_DUMMY2_RESET                          0
#define BB_CHN1_TABLES_DUMMY_2_ADDRESS                               0x0100
#define BB_CHN1_TABLES_DUMMY_2_HW_MASK                               0xffffffff
#define BB_CHN1_TABLES_DUMMY_2_SW_MASK                               0xffffffff
#define BB_CHN1_TABLES_DUMMY_2_HW_WRITE_MASK                         0x00000000
#define BB_CHN1_TABLES_DUMMY_2_SW_WRITE_MASK                         0xffffffff
#define BB_CHN1_TABLES_DUMMY_2_RSTMASK                               0x00000000
#define BB_CHN1_TABLES_DUMMY_2_RESET                                 0x00000000

// 0x0890 (BB_TXIQ_CORR_COEFF_0_B1)
#define BB_TXIQ_CORR_COEFF_0_B1_IQC_COEFF_TABLE_0_1_MSB              17
#define BB_TXIQ_CORR_COEFF_0_B1_IQC_COEFF_TABLE_0_1_LSB              0
#define BB_TXIQ_CORR_COEFF_0_B1_IQC_COEFF_TABLE_0_1_MASK             0x0003ffff
#define BB_TXIQ_CORR_COEFF_0_B1_IQC_COEFF_TABLE_0_1_GET(x)           (((x) & BB_TXIQ_CORR_COEFF_0_B1_IQC_COEFF_TABLE_0_1_MASK) >> BB_TXIQ_CORR_COEFF_0_B1_IQC_COEFF_TABLE_0_1_LSB)
#define BB_TXIQ_CORR_COEFF_0_B1_IQC_COEFF_TABLE_0_1_SET(x)           (((0 | (x)) << BB_TXIQ_CORR_COEFF_0_B1_IQC_COEFF_TABLE_0_1_LSB) & BB_TXIQ_CORR_COEFF_0_B1_IQC_COEFF_TABLE_0_1_MASK)
#define BB_TXIQ_CORR_COEFF_0_B1_IQC_COEFF_TABLE_0_1_RESET            0
#define BB_TXIQ_CORR_COEFF_0_B1_ADDRESS                              0x0890
#define BB_TXIQ_CORR_COEFF_0_B1_HW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_0_B1_SW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_0_B1_HW_WRITE_MASK                        0x00000000
#define BB_TXIQ_CORR_COEFF_0_B1_SW_WRITE_MASK                        0x0003ffff
#define BB_TXIQ_CORR_COEFF_0_B1_RSTMASK                              0xffffffff
#define BB_TXIQ_CORR_COEFF_0_B1_RESET                                0x00000000

// 0x0894 (BB_TXIQ_CORR_COEFF_1_B1)
#define BB_TXIQ_CORR_COEFF_1_B1_IQC_COEFF_TABLE_1_1_MSB              17
#define BB_TXIQ_CORR_COEFF_1_B1_IQC_COEFF_TABLE_1_1_LSB              0
#define BB_TXIQ_CORR_COEFF_1_B1_IQC_COEFF_TABLE_1_1_MASK             0x0003ffff
#define BB_TXIQ_CORR_COEFF_1_B1_IQC_COEFF_TABLE_1_1_GET(x)           (((x) & BB_TXIQ_CORR_COEFF_1_B1_IQC_COEFF_TABLE_1_1_MASK) >> BB_TXIQ_CORR_COEFF_1_B1_IQC_COEFF_TABLE_1_1_LSB)
#define BB_TXIQ_CORR_COEFF_1_B1_IQC_COEFF_TABLE_1_1_SET(x)           (((0 | (x)) << BB_TXIQ_CORR_COEFF_1_B1_IQC_COEFF_TABLE_1_1_LSB) & BB_TXIQ_CORR_COEFF_1_B1_IQC_COEFF_TABLE_1_1_MASK)
#define BB_TXIQ_CORR_COEFF_1_B1_IQC_COEFF_TABLE_1_1_RESET            0
#define BB_TXIQ_CORR_COEFF_1_B1_ADDRESS                              0x0894
#define BB_TXIQ_CORR_COEFF_1_B1_HW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_1_B1_SW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_1_B1_HW_WRITE_MASK                        0x00000000
#define BB_TXIQ_CORR_COEFF_1_B1_SW_WRITE_MASK                        0x0003ffff
#define BB_TXIQ_CORR_COEFF_1_B1_RSTMASK                              0xffffffff
#define BB_TXIQ_CORR_COEFF_1_B1_RESET                                0x00000000

// 0x0898 (BB_TXIQ_CORR_COEFF_2_B1)
#define BB_TXIQ_CORR_COEFF_2_B1_IQC_COEFF_TABLE_2_1_MSB              17
#define BB_TXIQ_CORR_COEFF_2_B1_IQC_COEFF_TABLE_2_1_LSB              0
#define BB_TXIQ_CORR_COEFF_2_B1_IQC_COEFF_TABLE_2_1_MASK             0x0003ffff
#define BB_TXIQ_CORR_COEFF_2_B1_IQC_COEFF_TABLE_2_1_GET(x)           (((x) & BB_TXIQ_CORR_COEFF_2_B1_IQC_COEFF_TABLE_2_1_MASK) >> BB_TXIQ_CORR_COEFF_2_B1_IQC_COEFF_TABLE_2_1_LSB)
#define BB_TXIQ_CORR_COEFF_2_B1_IQC_COEFF_TABLE_2_1_SET(x)           (((0 | (x)) << BB_TXIQ_CORR_COEFF_2_B1_IQC_COEFF_TABLE_2_1_LSB) & BB_TXIQ_CORR_COEFF_2_B1_IQC_COEFF_TABLE_2_1_MASK)
#define BB_TXIQ_CORR_COEFF_2_B1_IQC_COEFF_TABLE_2_1_RESET            0
#define BB_TXIQ_CORR_COEFF_2_B1_ADDRESS                              0x0898
#define BB_TXIQ_CORR_COEFF_2_B1_HW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_2_B1_SW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_2_B1_HW_WRITE_MASK                        0x00000000
#define BB_TXIQ_CORR_COEFF_2_B1_SW_WRITE_MASK                        0x0003ffff
#define BB_TXIQ_CORR_COEFF_2_B1_RSTMASK                              0xffffffff
#define BB_TXIQ_CORR_COEFF_2_B1_RESET                                0x00000000

// 0x089c (BB_TXIQ_CORR_COEFF_3_B1)
#define BB_TXIQ_CORR_COEFF_3_B1_IQC_COEFF_TABLE_3_1_MSB              17
#define BB_TXIQ_CORR_COEFF_3_B1_IQC_COEFF_TABLE_3_1_LSB              0
#define BB_TXIQ_CORR_COEFF_3_B1_IQC_COEFF_TABLE_3_1_MASK             0x0003ffff
#define BB_TXIQ_CORR_COEFF_3_B1_IQC_COEFF_TABLE_3_1_GET(x)           (((x) & BB_TXIQ_CORR_COEFF_3_B1_IQC_COEFF_TABLE_3_1_MASK) >> BB_TXIQ_CORR_COEFF_3_B1_IQC_COEFF_TABLE_3_1_LSB)
#define BB_TXIQ_CORR_COEFF_3_B1_IQC_COEFF_TABLE_3_1_SET(x)           (((0 | (x)) << BB_TXIQ_CORR_COEFF_3_B1_IQC_COEFF_TABLE_3_1_LSB) & BB_TXIQ_CORR_COEFF_3_B1_IQC_COEFF_TABLE_3_1_MASK)
#define BB_TXIQ_CORR_COEFF_3_B1_IQC_COEFF_TABLE_3_1_RESET            0
#define BB_TXIQ_CORR_COEFF_3_B1_ADDRESS                              0x089c
#define BB_TXIQ_CORR_COEFF_3_B1_HW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_3_B1_SW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_3_B1_HW_WRITE_MASK                        0x00000000
#define BB_TXIQ_CORR_COEFF_3_B1_SW_WRITE_MASK                        0x0003ffff
#define BB_TXIQ_CORR_COEFF_3_B1_RSTMASK                              0xffffffff
#define BB_TXIQ_CORR_COEFF_3_B1_RESET                                0x00000000

// 0x08a0 (BB_TXIQ_CORR_COEFF_4_B1)
#define BB_TXIQ_CORR_COEFF_4_B1_IQC_COEFF_TABLE_4_1_MSB              17
#define BB_TXIQ_CORR_COEFF_4_B1_IQC_COEFF_TABLE_4_1_LSB              0
#define BB_TXIQ_CORR_COEFF_4_B1_IQC_COEFF_TABLE_4_1_MASK             0x0003ffff
#define BB_TXIQ_CORR_COEFF_4_B1_IQC_COEFF_TABLE_4_1_GET(x)           (((x) & BB_TXIQ_CORR_COEFF_4_B1_IQC_COEFF_TABLE_4_1_MASK) >> BB_TXIQ_CORR_COEFF_4_B1_IQC_COEFF_TABLE_4_1_LSB)
#define BB_TXIQ_CORR_COEFF_4_B1_IQC_COEFF_TABLE_4_1_SET(x)           (((0 | (x)) << BB_TXIQ_CORR_COEFF_4_B1_IQC_COEFF_TABLE_4_1_LSB) & BB_TXIQ_CORR_COEFF_4_B1_IQC_COEFF_TABLE_4_1_MASK)
#define BB_TXIQ_CORR_COEFF_4_B1_IQC_COEFF_TABLE_4_1_RESET            0
#define BB_TXIQ_CORR_COEFF_4_B1_ADDRESS                              0x08a0
#define BB_TXIQ_CORR_COEFF_4_B1_HW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_4_B1_SW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_4_B1_HW_WRITE_MASK                        0x00000000
#define BB_TXIQ_CORR_COEFF_4_B1_SW_WRITE_MASK                        0x0003ffff
#define BB_TXIQ_CORR_COEFF_4_B1_RSTMASK                              0xffffffff
#define BB_TXIQ_CORR_COEFF_4_B1_RESET                                0x00000000

// 0x08a4 (BB_TXIQ_CORR_COEFF_5_B1)
#define BB_TXIQ_CORR_COEFF_5_B1_IQC_COEFF_TABLE_5_1_MSB              17
#define BB_TXIQ_CORR_COEFF_5_B1_IQC_COEFF_TABLE_5_1_LSB              0
#define BB_TXIQ_CORR_COEFF_5_B1_IQC_COEFF_TABLE_5_1_MASK             0x0003ffff
#define BB_TXIQ_CORR_COEFF_5_B1_IQC_COEFF_TABLE_5_1_GET(x)           (((x) & BB_TXIQ_CORR_COEFF_5_B1_IQC_COEFF_TABLE_5_1_MASK) >> BB_TXIQ_CORR_COEFF_5_B1_IQC_COEFF_TABLE_5_1_LSB)
#define BB_TXIQ_CORR_COEFF_5_B1_IQC_COEFF_TABLE_5_1_SET(x)           (((0 | (x)) << BB_TXIQ_CORR_COEFF_5_B1_IQC_COEFF_TABLE_5_1_LSB) & BB_TXIQ_CORR_COEFF_5_B1_IQC_COEFF_TABLE_5_1_MASK)
#define BB_TXIQ_CORR_COEFF_5_B1_IQC_COEFF_TABLE_5_1_RESET            0
#define BB_TXIQ_CORR_COEFF_5_B1_ADDRESS                              0x08a4
#define BB_TXIQ_CORR_COEFF_5_B1_HW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_5_B1_SW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_5_B1_HW_WRITE_MASK                        0x00000000
#define BB_TXIQ_CORR_COEFF_5_B1_SW_WRITE_MASK                        0x0003ffff
#define BB_TXIQ_CORR_COEFF_5_B1_RSTMASK                              0xffffffff
#define BB_TXIQ_CORR_COEFF_5_B1_RESET                                0x00000000

// 0x08a8 (BB_TXIQ_CORR_COEFF_6_B1)
#define BB_TXIQ_CORR_COEFF_6_B1_IQC_COEFF_TABLE_6_1_MSB              17
#define BB_TXIQ_CORR_COEFF_6_B1_IQC_COEFF_TABLE_6_1_LSB              0
#define BB_TXIQ_CORR_COEFF_6_B1_IQC_COEFF_TABLE_6_1_MASK             0x0003ffff
#define BB_TXIQ_CORR_COEFF_6_B1_IQC_COEFF_TABLE_6_1_GET(x)           (((x) & BB_TXIQ_CORR_COEFF_6_B1_IQC_COEFF_TABLE_6_1_MASK) >> BB_TXIQ_CORR_COEFF_6_B1_IQC_COEFF_TABLE_6_1_LSB)
#define BB_TXIQ_CORR_COEFF_6_B1_IQC_COEFF_TABLE_6_1_SET(x)           (((0 | (x)) << BB_TXIQ_CORR_COEFF_6_B1_IQC_COEFF_TABLE_6_1_LSB) & BB_TXIQ_CORR_COEFF_6_B1_IQC_COEFF_TABLE_6_1_MASK)
#define BB_TXIQ_CORR_COEFF_6_B1_IQC_COEFF_TABLE_6_1_RESET            0
#define BB_TXIQ_CORR_COEFF_6_B1_ADDRESS                              0x08a8
#define BB_TXIQ_CORR_COEFF_6_B1_HW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_6_B1_SW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_6_B1_HW_WRITE_MASK                        0x00000000
#define BB_TXIQ_CORR_COEFF_6_B1_SW_WRITE_MASK                        0x0003ffff
#define BB_TXIQ_CORR_COEFF_6_B1_RSTMASK                              0xffffffff
#define BB_TXIQ_CORR_COEFF_6_B1_RESET                                0x00000000

// 0x08ac (BB_TXIQ_CORR_COEFF_7_B1)
#define BB_TXIQ_CORR_COEFF_7_B1_IQC_COEFF_TABLE_7_1_MSB              17
#define BB_TXIQ_CORR_COEFF_7_B1_IQC_COEFF_TABLE_7_1_LSB              0
#define BB_TXIQ_CORR_COEFF_7_B1_IQC_COEFF_TABLE_7_1_MASK             0x0003ffff
#define BB_TXIQ_CORR_COEFF_7_B1_IQC_COEFF_TABLE_7_1_GET(x)           (((x) & BB_TXIQ_CORR_COEFF_7_B1_IQC_COEFF_TABLE_7_1_MASK) >> BB_TXIQ_CORR_COEFF_7_B1_IQC_COEFF_TABLE_7_1_LSB)
#define BB_TXIQ_CORR_COEFF_7_B1_IQC_COEFF_TABLE_7_1_SET(x)           (((0 | (x)) << BB_TXIQ_CORR_COEFF_7_B1_IQC_COEFF_TABLE_7_1_LSB) & BB_TXIQ_CORR_COEFF_7_B1_IQC_COEFF_TABLE_7_1_MASK)
#define BB_TXIQ_CORR_COEFF_7_B1_IQC_COEFF_TABLE_7_1_RESET            0
#define BB_TXIQ_CORR_COEFF_7_B1_ADDRESS                              0x08ac
#define BB_TXIQ_CORR_COEFF_7_B1_HW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_7_B1_SW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_7_B1_HW_WRITE_MASK                        0x00000000
#define BB_TXIQ_CORR_COEFF_7_B1_SW_WRITE_MASK                        0x0003ffff
#define BB_TXIQ_CORR_COEFF_7_B1_RSTMASK                              0xffffffff
#define BB_TXIQ_CORR_COEFF_7_B1_RESET                                0x00000000

// 0x08b0 (BB_TXIQ_CORR_COEFF_8_B1)
#define BB_TXIQ_CORR_COEFF_8_B1_IQC_COEFF_TABLE_8_1_MSB              17
#define BB_TXIQ_CORR_COEFF_8_B1_IQC_COEFF_TABLE_8_1_LSB              0
#define BB_TXIQ_CORR_COEFF_8_B1_IQC_COEFF_TABLE_8_1_MASK             0x0003ffff
#define BB_TXIQ_CORR_COEFF_8_B1_IQC_COEFF_TABLE_8_1_GET(x)           (((x) & BB_TXIQ_CORR_COEFF_8_B1_IQC_COEFF_TABLE_8_1_MASK) >> BB_TXIQ_CORR_COEFF_8_B1_IQC_COEFF_TABLE_8_1_LSB)
#define BB_TXIQ_CORR_COEFF_8_B1_IQC_COEFF_TABLE_8_1_SET(x)           (((0 | (x)) << BB_TXIQ_CORR_COEFF_8_B1_IQC_COEFF_TABLE_8_1_LSB) & BB_TXIQ_CORR_COEFF_8_B1_IQC_COEFF_TABLE_8_1_MASK)
#define BB_TXIQ_CORR_COEFF_8_B1_IQC_COEFF_TABLE_8_1_RESET            0
#define BB_TXIQ_CORR_COEFF_8_B1_ADDRESS                              0x08b0
#define BB_TXIQ_CORR_COEFF_8_B1_HW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_8_B1_SW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_8_B1_HW_WRITE_MASK                        0x00000000
#define BB_TXIQ_CORR_COEFF_8_B1_SW_WRITE_MASK                        0x0003ffff
#define BB_TXIQ_CORR_COEFF_8_B1_RSTMASK                              0xffffffff
#define BB_TXIQ_CORR_COEFF_8_B1_RESET                                0x00000000

// 0x08b4 (BB_TXIQ_CORR_COEFF_9_B1)
#define BB_TXIQ_CORR_COEFF_9_B1_IQC_COEFF_TABLE_9_1_MSB              17
#define BB_TXIQ_CORR_COEFF_9_B1_IQC_COEFF_TABLE_9_1_LSB              0
#define BB_TXIQ_CORR_COEFF_9_B1_IQC_COEFF_TABLE_9_1_MASK             0x0003ffff
#define BB_TXIQ_CORR_COEFF_9_B1_IQC_COEFF_TABLE_9_1_GET(x)           (((x) & BB_TXIQ_CORR_COEFF_9_B1_IQC_COEFF_TABLE_9_1_MASK) >> BB_TXIQ_CORR_COEFF_9_B1_IQC_COEFF_TABLE_9_1_LSB)
#define BB_TXIQ_CORR_COEFF_9_B1_IQC_COEFF_TABLE_9_1_SET(x)           (((0 | (x)) << BB_TXIQ_CORR_COEFF_9_B1_IQC_COEFF_TABLE_9_1_LSB) & BB_TXIQ_CORR_COEFF_9_B1_IQC_COEFF_TABLE_9_1_MASK)
#define BB_TXIQ_CORR_COEFF_9_B1_IQC_COEFF_TABLE_9_1_RESET            0
#define BB_TXIQ_CORR_COEFF_9_B1_ADDRESS                              0x08b4
#define BB_TXIQ_CORR_COEFF_9_B1_HW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_9_B1_SW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_9_B1_HW_WRITE_MASK                        0x00000000
#define BB_TXIQ_CORR_COEFF_9_B1_SW_WRITE_MASK                        0x0003ffff
#define BB_TXIQ_CORR_COEFF_9_B1_RSTMASK                              0xffffffff
#define BB_TXIQ_CORR_COEFF_9_B1_RESET                                0x00000000

// 0x08b8 (BB_TXIQ_CORR_COEFF_A_B1)
#define BB_TXIQ_CORR_COEFF_A_B1_IQC_COEFF_TABLE_A_1_MSB              17
#define BB_TXIQ_CORR_COEFF_A_B1_IQC_COEFF_TABLE_A_1_LSB              0
#define BB_TXIQ_CORR_COEFF_A_B1_IQC_COEFF_TABLE_A_1_MASK             0x0003ffff
#define BB_TXIQ_CORR_COEFF_A_B1_IQC_COEFF_TABLE_A_1_GET(x)           (((x) & BB_TXIQ_CORR_COEFF_A_B1_IQC_COEFF_TABLE_A_1_MASK) >> BB_TXIQ_CORR_COEFF_A_B1_IQC_COEFF_TABLE_A_1_LSB)
#define BB_TXIQ_CORR_COEFF_A_B1_IQC_COEFF_TABLE_A_1_SET(x)           (((0 | (x)) << BB_TXIQ_CORR_COEFF_A_B1_IQC_COEFF_TABLE_A_1_LSB) & BB_TXIQ_CORR_COEFF_A_B1_IQC_COEFF_TABLE_A_1_MASK)
#define BB_TXIQ_CORR_COEFF_A_B1_IQC_COEFF_TABLE_A_1_RESET            0
#define BB_TXIQ_CORR_COEFF_A_B1_ADDRESS                              0x08b8
#define BB_TXIQ_CORR_COEFF_A_B1_HW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_A_B1_SW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_A_B1_HW_WRITE_MASK                        0x00000000
#define BB_TXIQ_CORR_COEFF_A_B1_SW_WRITE_MASK                        0x0003ffff
#define BB_TXIQ_CORR_COEFF_A_B1_RSTMASK                              0xffffffff
#define BB_TXIQ_CORR_COEFF_A_B1_RESET                                0x00000000

// 0x08bc (BB_TXIQ_CORR_COEFF_B_B1)
#define BB_TXIQ_CORR_COEFF_B_B1_IQC_COEFF_TABLE_B_1_MSB              17
#define BB_TXIQ_CORR_COEFF_B_B1_IQC_COEFF_TABLE_B_1_LSB              0
#define BB_TXIQ_CORR_COEFF_B_B1_IQC_COEFF_TABLE_B_1_MASK             0x0003ffff
#define BB_TXIQ_CORR_COEFF_B_B1_IQC_COEFF_TABLE_B_1_GET(x)           (((x) & BB_TXIQ_CORR_COEFF_B_B1_IQC_COEFF_TABLE_B_1_MASK) >> BB_TXIQ_CORR_COEFF_B_B1_IQC_COEFF_TABLE_B_1_LSB)
#define BB_TXIQ_CORR_COEFF_B_B1_IQC_COEFF_TABLE_B_1_SET(x)           (((0 | (x)) << BB_TXIQ_CORR_COEFF_B_B1_IQC_COEFF_TABLE_B_1_LSB) & BB_TXIQ_CORR_COEFF_B_B1_IQC_COEFF_TABLE_B_1_MASK)
#define BB_TXIQ_CORR_COEFF_B_B1_IQC_COEFF_TABLE_B_1_RESET            0
#define BB_TXIQ_CORR_COEFF_B_B1_ADDRESS                              0x08bc
#define BB_TXIQ_CORR_COEFF_B_B1_HW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_B_B1_SW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_B_B1_HW_WRITE_MASK                        0x00000000
#define BB_TXIQ_CORR_COEFF_B_B1_SW_WRITE_MASK                        0x0003ffff
#define BB_TXIQ_CORR_COEFF_B_B1_RSTMASK                              0xffffffff
#define BB_TXIQ_CORR_COEFF_B_B1_RESET                                0x00000000

// 0x08c0 (BB_TXIQ_CORR_COEFF_C_B1)
#define BB_TXIQ_CORR_COEFF_C_B1_IQC_COEFF_TABLE_C_1_MSB              17
#define BB_TXIQ_CORR_COEFF_C_B1_IQC_COEFF_TABLE_C_1_LSB              0
#define BB_TXIQ_CORR_COEFF_C_B1_IQC_COEFF_TABLE_C_1_MASK             0x0003ffff
#define BB_TXIQ_CORR_COEFF_C_B1_IQC_COEFF_TABLE_C_1_GET(x)           (((x) & BB_TXIQ_CORR_COEFF_C_B1_IQC_COEFF_TABLE_C_1_MASK) >> BB_TXIQ_CORR_COEFF_C_B1_IQC_COEFF_TABLE_C_1_LSB)
#define BB_TXIQ_CORR_COEFF_C_B1_IQC_COEFF_TABLE_C_1_SET(x)           (((0 | (x)) << BB_TXIQ_CORR_COEFF_C_B1_IQC_COEFF_TABLE_C_1_LSB) & BB_TXIQ_CORR_COEFF_C_B1_IQC_COEFF_TABLE_C_1_MASK)
#define BB_TXIQ_CORR_COEFF_C_B1_IQC_COEFF_TABLE_C_1_RESET            0
#define BB_TXIQ_CORR_COEFF_C_B1_ADDRESS                              0x08c0
#define BB_TXIQ_CORR_COEFF_C_B1_HW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_C_B1_SW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_C_B1_HW_WRITE_MASK                        0x00000000
#define BB_TXIQ_CORR_COEFF_C_B1_SW_WRITE_MASK                        0x0003ffff
#define BB_TXIQ_CORR_COEFF_C_B1_RSTMASK                              0xffffffff
#define BB_TXIQ_CORR_COEFF_C_B1_RESET                                0x00000000

// 0x08c4 (BB_TXIQ_CORR_COEFF_D_B1)
#define BB_TXIQ_CORR_COEFF_D_B1_IQC_COEFF_TABLE_D_1_MSB              17
#define BB_TXIQ_CORR_COEFF_D_B1_IQC_COEFF_TABLE_D_1_LSB              0
#define BB_TXIQ_CORR_COEFF_D_B1_IQC_COEFF_TABLE_D_1_MASK             0x0003ffff
#define BB_TXIQ_CORR_COEFF_D_B1_IQC_COEFF_TABLE_D_1_GET(x)           (((x) & BB_TXIQ_CORR_COEFF_D_B1_IQC_COEFF_TABLE_D_1_MASK) >> BB_TXIQ_CORR_COEFF_D_B1_IQC_COEFF_TABLE_D_1_LSB)
#define BB_TXIQ_CORR_COEFF_D_B1_IQC_COEFF_TABLE_D_1_SET(x)           (((0 | (x)) << BB_TXIQ_CORR_COEFF_D_B1_IQC_COEFF_TABLE_D_1_LSB) & BB_TXIQ_CORR_COEFF_D_B1_IQC_COEFF_TABLE_D_1_MASK)
#define BB_TXIQ_CORR_COEFF_D_B1_IQC_COEFF_TABLE_D_1_RESET            0
#define BB_TXIQ_CORR_COEFF_D_B1_ADDRESS                              0x08c4
#define BB_TXIQ_CORR_COEFF_D_B1_HW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_D_B1_SW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_D_B1_HW_WRITE_MASK                        0x00000000
#define BB_TXIQ_CORR_COEFF_D_B1_SW_WRITE_MASK                        0x0003ffff
#define BB_TXIQ_CORR_COEFF_D_B1_RSTMASK                              0xffffffff
#define BB_TXIQ_CORR_COEFF_D_B1_RESET                                0x00000000

// 0x08c8 (BB_TXIQ_CORR_COEFF_E_B1)
#define BB_TXIQ_CORR_COEFF_E_B1_IQC_COEFF_TABLE_E_1_MSB              17
#define BB_TXIQ_CORR_COEFF_E_B1_IQC_COEFF_TABLE_E_1_LSB              0
#define BB_TXIQ_CORR_COEFF_E_B1_IQC_COEFF_TABLE_E_1_MASK             0x0003ffff
#define BB_TXIQ_CORR_COEFF_E_B1_IQC_COEFF_TABLE_E_1_GET(x)           (((x) & BB_TXIQ_CORR_COEFF_E_B1_IQC_COEFF_TABLE_E_1_MASK) >> BB_TXIQ_CORR_COEFF_E_B1_IQC_COEFF_TABLE_E_1_LSB)
#define BB_TXIQ_CORR_COEFF_E_B1_IQC_COEFF_TABLE_E_1_SET(x)           (((0 | (x)) << BB_TXIQ_CORR_COEFF_E_B1_IQC_COEFF_TABLE_E_1_LSB) & BB_TXIQ_CORR_COEFF_E_B1_IQC_COEFF_TABLE_E_1_MASK)
#define BB_TXIQ_CORR_COEFF_E_B1_IQC_COEFF_TABLE_E_1_RESET            0
#define BB_TXIQ_CORR_COEFF_E_B1_ADDRESS                              0x08c8
#define BB_TXIQ_CORR_COEFF_E_B1_HW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_E_B1_SW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_E_B1_HW_WRITE_MASK                        0x00000000
#define BB_TXIQ_CORR_COEFF_E_B1_SW_WRITE_MASK                        0x0003ffff
#define BB_TXIQ_CORR_COEFF_E_B1_RSTMASK                              0xffffffff
#define BB_TXIQ_CORR_COEFF_E_B1_RESET                                0x00000000

// 0x08cc (BB_TXIQ_CORR_COEFF_F_B1)
#define BB_TXIQ_CORR_COEFF_F_B1_IQC_COEFF_TABLE_F_1_MSB              17
#define BB_TXIQ_CORR_COEFF_F_B1_IQC_COEFF_TABLE_F_1_LSB              0
#define BB_TXIQ_CORR_COEFF_F_B1_IQC_COEFF_TABLE_F_1_MASK             0x0003ffff
#define BB_TXIQ_CORR_COEFF_F_B1_IQC_COEFF_TABLE_F_1_GET(x)           (((x) & BB_TXIQ_CORR_COEFF_F_B1_IQC_COEFF_TABLE_F_1_MASK) >> BB_TXIQ_CORR_COEFF_F_B1_IQC_COEFF_TABLE_F_1_LSB)
#define BB_TXIQ_CORR_COEFF_F_B1_IQC_COEFF_TABLE_F_1_SET(x)           (((0 | (x)) << BB_TXIQ_CORR_COEFF_F_B1_IQC_COEFF_TABLE_F_1_LSB) & BB_TXIQ_CORR_COEFF_F_B1_IQC_COEFF_TABLE_F_1_MASK)
#define BB_TXIQ_CORR_COEFF_F_B1_IQC_COEFF_TABLE_F_1_RESET            0
#define BB_TXIQ_CORR_COEFF_F_B1_ADDRESS                              0x08cc
#define BB_TXIQ_CORR_COEFF_F_B1_HW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_F_B1_SW_MASK                              0x0003ffff
#define BB_TXIQ_CORR_COEFF_F_B1_HW_WRITE_MASK                        0x00000000
#define BB_TXIQ_CORR_COEFF_F_B1_SW_WRITE_MASK                        0x0003ffff
#define BB_TXIQ_CORR_COEFF_F_B1_RSTMASK                              0xffffffff
#define BB_TXIQ_CORR_COEFF_F_B1_RESET                                0x00000000

// 0x08d0 (BB_RXCAL_TXIQCORR_COEF_0_B1)
#define BB_RXCAL_TXIQCORR_COEF_0_B1_RXCAL_TXIQCORR_COEF_0_CHN1_MSB   17
#define BB_RXCAL_TXIQCORR_COEF_0_B1_RXCAL_TXIQCORR_COEF_0_CHN1_LSB   0
#define BB_RXCAL_TXIQCORR_COEF_0_B1_RXCAL_TXIQCORR_COEF_0_CHN1_MASK  0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_0_B1_RXCAL_TXIQCORR_COEF_0_CHN1_GET(x) (((x) & BB_RXCAL_TXIQCORR_COEF_0_B1_RXCAL_TXIQCORR_COEF_0_CHN1_MASK) >> BB_RXCAL_TXIQCORR_COEF_0_B1_RXCAL_TXIQCORR_COEF_0_CHN1_LSB)
#define BB_RXCAL_TXIQCORR_COEF_0_B1_RXCAL_TXIQCORR_COEF_0_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TXIQCORR_COEF_0_B1_RXCAL_TXIQCORR_COEF_0_CHN1_LSB) & BB_RXCAL_TXIQCORR_COEF_0_B1_RXCAL_TXIQCORR_COEF_0_CHN1_MASK)
#define BB_RXCAL_TXIQCORR_COEF_0_B1_RXCAL_TXIQCORR_COEF_0_CHN1_RESET 0
#define BB_RXCAL_TXIQCORR_COEF_0_B1_ADDRESS                          0x08d0
#define BB_RXCAL_TXIQCORR_COEF_0_B1_HW_MASK                          0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_0_B1_SW_MASK                          0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_0_B1_HW_WRITE_MASK                    0x00000000
#define BB_RXCAL_TXIQCORR_COEF_0_B1_SW_WRITE_MASK                    0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_0_B1_RSTMASK                          0xffffffff
#define BB_RXCAL_TXIQCORR_COEF_0_B1_RESET                            0x00000000

// 0x08d4 (BB_RXCAL_TXIQCORR_COEF_1_B1)
#define BB_RXCAL_TXIQCORR_COEF_1_B1_RXCAL_TXIQCORR_COEF_1_CHN1_MSB   17
#define BB_RXCAL_TXIQCORR_COEF_1_B1_RXCAL_TXIQCORR_COEF_1_CHN1_LSB   0
#define BB_RXCAL_TXIQCORR_COEF_1_B1_RXCAL_TXIQCORR_COEF_1_CHN1_MASK  0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_1_B1_RXCAL_TXIQCORR_COEF_1_CHN1_GET(x) (((x) & BB_RXCAL_TXIQCORR_COEF_1_B1_RXCAL_TXIQCORR_COEF_1_CHN1_MASK) >> BB_RXCAL_TXIQCORR_COEF_1_B1_RXCAL_TXIQCORR_COEF_1_CHN1_LSB)
#define BB_RXCAL_TXIQCORR_COEF_1_B1_RXCAL_TXIQCORR_COEF_1_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TXIQCORR_COEF_1_B1_RXCAL_TXIQCORR_COEF_1_CHN1_LSB) & BB_RXCAL_TXIQCORR_COEF_1_B1_RXCAL_TXIQCORR_COEF_1_CHN1_MASK)
#define BB_RXCAL_TXIQCORR_COEF_1_B1_RXCAL_TXIQCORR_COEF_1_CHN1_RESET 0
#define BB_RXCAL_TXIQCORR_COEF_1_B1_ADDRESS                          0x08d4
#define BB_RXCAL_TXIQCORR_COEF_1_B1_HW_MASK                          0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_1_B1_SW_MASK                          0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_1_B1_HW_WRITE_MASK                    0x00000000
#define BB_RXCAL_TXIQCORR_COEF_1_B1_SW_WRITE_MASK                    0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_1_B1_RSTMASK                          0xffffffff
#define BB_RXCAL_TXIQCORR_COEF_1_B1_RESET                            0x00000000

// 0x08d8 (BB_RXCAL_TXIQCORR_COEF_2_B1)
#define BB_RXCAL_TXIQCORR_COEF_2_B1_RXCAL_TXIQCORR_COEF_2_CHN1_MSB   17
#define BB_RXCAL_TXIQCORR_COEF_2_B1_RXCAL_TXIQCORR_COEF_2_CHN1_LSB   0
#define BB_RXCAL_TXIQCORR_COEF_2_B1_RXCAL_TXIQCORR_COEF_2_CHN1_MASK  0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_2_B1_RXCAL_TXIQCORR_COEF_2_CHN1_GET(x) (((x) & BB_RXCAL_TXIQCORR_COEF_2_B1_RXCAL_TXIQCORR_COEF_2_CHN1_MASK) >> BB_RXCAL_TXIQCORR_COEF_2_B1_RXCAL_TXIQCORR_COEF_2_CHN1_LSB)
#define BB_RXCAL_TXIQCORR_COEF_2_B1_RXCAL_TXIQCORR_COEF_2_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TXIQCORR_COEF_2_B1_RXCAL_TXIQCORR_COEF_2_CHN1_LSB) & BB_RXCAL_TXIQCORR_COEF_2_B1_RXCAL_TXIQCORR_COEF_2_CHN1_MASK)
#define BB_RXCAL_TXIQCORR_COEF_2_B1_RXCAL_TXIQCORR_COEF_2_CHN1_RESET 0
#define BB_RXCAL_TXIQCORR_COEF_2_B1_ADDRESS                          0x08d8
#define BB_RXCAL_TXIQCORR_COEF_2_B1_HW_MASK                          0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_2_B1_SW_MASK                          0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_2_B1_HW_WRITE_MASK                    0x00000000
#define BB_RXCAL_TXIQCORR_COEF_2_B1_SW_WRITE_MASK                    0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_2_B1_RSTMASK                          0xffffffff
#define BB_RXCAL_TXIQCORR_COEF_2_B1_RESET                            0x00000000

// 0x08dc (BB_RXCAL_TXIQCORR_COEF_3_B1)
#define BB_RXCAL_TXIQCORR_COEF_3_B1_RXCAL_TXIQCORR_COEF_3_CHN1_MSB   17
#define BB_RXCAL_TXIQCORR_COEF_3_B1_RXCAL_TXIQCORR_COEF_3_CHN1_LSB   0
#define BB_RXCAL_TXIQCORR_COEF_3_B1_RXCAL_TXIQCORR_COEF_3_CHN1_MASK  0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_3_B1_RXCAL_TXIQCORR_COEF_3_CHN1_GET(x) (((x) & BB_RXCAL_TXIQCORR_COEF_3_B1_RXCAL_TXIQCORR_COEF_3_CHN1_MASK) >> BB_RXCAL_TXIQCORR_COEF_3_B1_RXCAL_TXIQCORR_COEF_3_CHN1_LSB)
#define BB_RXCAL_TXIQCORR_COEF_3_B1_RXCAL_TXIQCORR_COEF_3_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TXIQCORR_COEF_3_B1_RXCAL_TXIQCORR_COEF_3_CHN1_LSB) & BB_RXCAL_TXIQCORR_COEF_3_B1_RXCAL_TXIQCORR_COEF_3_CHN1_MASK)
#define BB_RXCAL_TXIQCORR_COEF_3_B1_RXCAL_TXIQCORR_COEF_3_CHN1_RESET 0
#define BB_RXCAL_TXIQCORR_COEF_3_B1_ADDRESS                          0x08dc
#define BB_RXCAL_TXIQCORR_COEF_3_B1_HW_MASK                          0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_3_B1_SW_MASK                          0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_3_B1_HW_WRITE_MASK                    0x00000000
#define BB_RXCAL_TXIQCORR_COEF_3_B1_SW_WRITE_MASK                    0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_3_B1_RSTMASK                          0xffffffff
#define BB_RXCAL_TXIQCORR_COEF_3_B1_RESET                            0x00000000

// 0x08e0 (BB_RXCAL_TXIQCORR_COEF_4_B1)
#define BB_RXCAL_TXIQCORR_COEF_4_B1_RXCAL_TXIQCORR_COEF_4_CHN1_MSB   17
#define BB_RXCAL_TXIQCORR_COEF_4_B1_RXCAL_TXIQCORR_COEF_4_CHN1_LSB   0
#define BB_RXCAL_TXIQCORR_COEF_4_B1_RXCAL_TXIQCORR_COEF_4_CHN1_MASK  0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_4_B1_RXCAL_TXIQCORR_COEF_4_CHN1_GET(x) (((x) & BB_RXCAL_TXIQCORR_COEF_4_B1_RXCAL_TXIQCORR_COEF_4_CHN1_MASK) >> BB_RXCAL_TXIQCORR_COEF_4_B1_RXCAL_TXIQCORR_COEF_4_CHN1_LSB)
#define BB_RXCAL_TXIQCORR_COEF_4_B1_RXCAL_TXIQCORR_COEF_4_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TXIQCORR_COEF_4_B1_RXCAL_TXIQCORR_COEF_4_CHN1_LSB) & BB_RXCAL_TXIQCORR_COEF_4_B1_RXCAL_TXIQCORR_COEF_4_CHN1_MASK)
#define BB_RXCAL_TXIQCORR_COEF_4_B1_RXCAL_TXIQCORR_COEF_4_CHN1_RESET 0
#define BB_RXCAL_TXIQCORR_COEF_4_B1_ADDRESS                          0x08e0
#define BB_RXCAL_TXIQCORR_COEF_4_B1_HW_MASK                          0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_4_B1_SW_MASK                          0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_4_B1_HW_WRITE_MASK                    0x00000000
#define BB_RXCAL_TXIQCORR_COEF_4_B1_SW_WRITE_MASK                    0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_4_B1_RSTMASK                          0xffffffff
#define BB_RXCAL_TXIQCORR_COEF_4_B1_RESET                            0x00000000

// 0x08e4 (BB_RXCAL_TXIQCORR_COEF_5_B1)
#define BB_RXCAL_TXIQCORR_COEF_5_B1_RXCAL_TXIQCORR_COEF_5_CHN1_MSB   17
#define BB_RXCAL_TXIQCORR_COEF_5_B1_RXCAL_TXIQCORR_COEF_5_CHN1_LSB   0
#define BB_RXCAL_TXIQCORR_COEF_5_B1_RXCAL_TXIQCORR_COEF_5_CHN1_MASK  0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_5_B1_RXCAL_TXIQCORR_COEF_5_CHN1_GET(x) (((x) & BB_RXCAL_TXIQCORR_COEF_5_B1_RXCAL_TXIQCORR_COEF_5_CHN1_MASK) >> BB_RXCAL_TXIQCORR_COEF_5_B1_RXCAL_TXIQCORR_COEF_5_CHN1_LSB)
#define BB_RXCAL_TXIQCORR_COEF_5_B1_RXCAL_TXIQCORR_COEF_5_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TXIQCORR_COEF_5_B1_RXCAL_TXIQCORR_COEF_5_CHN1_LSB) & BB_RXCAL_TXIQCORR_COEF_5_B1_RXCAL_TXIQCORR_COEF_5_CHN1_MASK)
#define BB_RXCAL_TXIQCORR_COEF_5_B1_RXCAL_TXIQCORR_COEF_5_CHN1_RESET 0
#define BB_RXCAL_TXIQCORR_COEF_5_B1_ADDRESS                          0x08e4
#define BB_RXCAL_TXIQCORR_COEF_5_B1_HW_MASK                          0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_5_B1_SW_MASK                          0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_5_B1_HW_WRITE_MASK                    0x00000000
#define BB_RXCAL_TXIQCORR_COEF_5_B1_SW_WRITE_MASK                    0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_5_B1_RSTMASK                          0xffffffff
#define BB_RXCAL_TXIQCORR_COEF_5_B1_RESET                            0x00000000

// 0x08e8 (BB_RXCAL_TXIQCORR_COEF_6_B1)
#define BB_RXCAL_TXIQCORR_COEF_6_B1_RXCAL_TXIQCORR_COEF_6_CHN1_MSB   17
#define BB_RXCAL_TXIQCORR_COEF_6_B1_RXCAL_TXIQCORR_COEF_6_CHN1_LSB   0
#define BB_RXCAL_TXIQCORR_COEF_6_B1_RXCAL_TXIQCORR_COEF_6_CHN1_MASK  0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_6_B1_RXCAL_TXIQCORR_COEF_6_CHN1_GET(x) (((x) & BB_RXCAL_TXIQCORR_COEF_6_B1_RXCAL_TXIQCORR_COEF_6_CHN1_MASK) >> BB_RXCAL_TXIQCORR_COEF_6_B1_RXCAL_TXIQCORR_COEF_6_CHN1_LSB)
#define BB_RXCAL_TXIQCORR_COEF_6_B1_RXCAL_TXIQCORR_COEF_6_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TXIQCORR_COEF_6_B1_RXCAL_TXIQCORR_COEF_6_CHN1_LSB) & BB_RXCAL_TXIQCORR_COEF_6_B1_RXCAL_TXIQCORR_COEF_6_CHN1_MASK)
#define BB_RXCAL_TXIQCORR_COEF_6_B1_RXCAL_TXIQCORR_COEF_6_CHN1_RESET 0
#define BB_RXCAL_TXIQCORR_COEF_6_B1_ADDRESS                          0x08e8
#define BB_RXCAL_TXIQCORR_COEF_6_B1_HW_MASK                          0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_6_B1_SW_MASK                          0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_6_B1_HW_WRITE_MASK                    0x00000000
#define BB_RXCAL_TXIQCORR_COEF_6_B1_SW_WRITE_MASK                    0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_6_B1_RSTMASK                          0xffffffff
#define BB_RXCAL_TXIQCORR_COEF_6_B1_RESET                            0x00000000

// 0x08ec (BB_RXCAL_TXIQCORR_COEF_7_B1)
#define BB_RXCAL_TXIQCORR_COEF_7_B1_RXCAL_TXIQCORR_COEF_7_CHN1_MSB   17
#define BB_RXCAL_TXIQCORR_COEF_7_B1_RXCAL_TXIQCORR_COEF_7_CHN1_LSB   0
#define BB_RXCAL_TXIQCORR_COEF_7_B1_RXCAL_TXIQCORR_COEF_7_CHN1_MASK  0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_7_B1_RXCAL_TXIQCORR_COEF_7_CHN1_GET(x) (((x) & BB_RXCAL_TXIQCORR_COEF_7_B1_RXCAL_TXIQCORR_COEF_7_CHN1_MASK) >> BB_RXCAL_TXIQCORR_COEF_7_B1_RXCAL_TXIQCORR_COEF_7_CHN1_LSB)
#define BB_RXCAL_TXIQCORR_COEF_7_B1_RXCAL_TXIQCORR_COEF_7_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TXIQCORR_COEF_7_B1_RXCAL_TXIQCORR_COEF_7_CHN1_LSB) & BB_RXCAL_TXIQCORR_COEF_7_B1_RXCAL_TXIQCORR_COEF_7_CHN1_MASK)
#define BB_RXCAL_TXIQCORR_COEF_7_B1_RXCAL_TXIQCORR_COEF_7_CHN1_RESET 0
#define BB_RXCAL_TXIQCORR_COEF_7_B1_ADDRESS                          0x08ec
#define BB_RXCAL_TXIQCORR_COEF_7_B1_HW_MASK                          0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_7_B1_SW_MASK                          0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_7_B1_HW_WRITE_MASK                    0x00000000
#define BB_RXCAL_TXIQCORR_COEF_7_B1_SW_WRITE_MASK                    0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_7_B1_RSTMASK                          0xffffffff
#define BB_RXCAL_TXIQCORR_COEF_7_B1_RESET                            0x00000000

// 0x08f0 (BB_RXCAL_TXIQCORR_COEF_8_B1)
#define BB_RXCAL_TXIQCORR_COEF_8_B1_RXCAL_TXIQCORR_COEF_8_CHN1_MSB   17
#define BB_RXCAL_TXIQCORR_COEF_8_B1_RXCAL_TXIQCORR_COEF_8_CHN1_LSB   0
#define BB_RXCAL_TXIQCORR_COEF_8_B1_RXCAL_TXIQCORR_COEF_8_CHN1_MASK  0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_8_B1_RXCAL_TXIQCORR_COEF_8_CHN1_GET(x) (((x) & BB_RXCAL_TXIQCORR_COEF_8_B1_RXCAL_TXIQCORR_COEF_8_CHN1_MASK) >> BB_RXCAL_TXIQCORR_COEF_8_B1_RXCAL_TXIQCORR_COEF_8_CHN1_LSB)
#define BB_RXCAL_TXIQCORR_COEF_8_B1_RXCAL_TXIQCORR_COEF_8_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TXIQCORR_COEF_8_B1_RXCAL_TXIQCORR_COEF_8_CHN1_LSB) & BB_RXCAL_TXIQCORR_COEF_8_B1_RXCAL_TXIQCORR_COEF_8_CHN1_MASK)
#define BB_RXCAL_TXIQCORR_COEF_8_B1_RXCAL_TXIQCORR_COEF_8_CHN1_RESET 0
#define BB_RXCAL_TXIQCORR_COEF_8_B1_ADDRESS                          0x08f0
#define BB_RXCAL_TXIQCORR_COEF_8_B1_HW_MASK                          0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_8_B1_SW_MASK                          0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_8_B1_HW_WRITE_MASK                    0x00000000
#define BB_RXCAL_TXIQCORR_COEF_8_B1_SW_WRITE_MASK                    0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_8_B1_RSTMASK                          0xffffffff
#define BB_RXCAL_TXIQCORR_COEF_8_B1_RESET                            0x00000000

// 0x08f4 (BB_RXCAL_TXIQCORR_COEF_9_B1)
#define BB_RXCAL_TXIQCORR_COEF_9_B1_RXCAL_TXIQCORR_COEF_9_CHN1_MSB   17
#define BB_RXCAL_TXIQCORR_COEF_9_B1_RXCAL_TXIQCORR_COEF_9_CHN1_LSB   0
#define BB_RXCAL_TXIQCORR_COEF_9_B1_RXCAL_TXIQCORR_COEF_9_CHN1_MASK  0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_9_B1_RXCAL_TXIQCORR_COEF_9_CHN1_GET(x) (((x) & BB_RXCAL_TXIQCORR_COEF_9_B1_RXCAL_TXIQCORR_COEF_9_CHN1_MASK) >> BB_RXCAL_TXIQCORR_COEF_9_B1_RXCAL_TXIQCORR_COEF_9_CHN1_LSB)
#define BB_RXCAL_TXIQCORR_COEF_9_B1_RXCAL_TXIQCORR_COEF_9_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TXIQCORR_COEF_9_B1_RXCAL_TXIQCORR_COEF_9_CHN1_LSB) & BB_RXCAL_TXIQCORR_COEF_9_B1_RXCAL_TXIQCORR_COEF_9_CHN1_MASK)
#define BB_RXCAL_TXIQCORR_COEF_9_B1_RXCAL_TXIQCORR_COEF_9_CHN1_RESET 0
#define BB_RXCAL_TXIQCORR_COEF_9_B1_ADDRESS                          0x08f4
#define BB_RXCAL_TXIQCORR_COEF_9_B1_HW_MASK                          0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_9_B1_SW_MASK                          0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_9_B1_HW_WRITE_MASK                    0x00000000
#define BB_RXCAL_TXIQCORR_COEF_9_B1_SW_WRITE_MASK                    0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_9_B1_RSTMASK                          0xffffffff
#define BB_RXCAL_TXIQCORR_COEF_9_B1_RESET                            0x00000000

// 0x08f8 (BB_RXCAL_TXIQCORR_COEF_10_B1)
#define BB_RXCAL_TXIQCORR_COEF_10_B1_RXCAL_TXIQCORR_COEF_10_CHN1_MSB 17
#define BB_RXCAL_TXIQCORR_COEF_10_B1_RXCAL_TXIQCORR_COEF_10_CHN1_LSB 0
#define BB_RXCAL_TXIQCORR_COEF_10_B1_RXCAL_TXIQCORR_COEF_10_CHN1_MASK 0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_10_B1_RXCAL_TXIQCORR_COEF_10_CHN1_GET(x) (((x) & BB_RXCAL_TXIQCORR_COEF_10_B1_RXCAL_TXIQCORR_COEF_10_CHN1_MASK) >> BB_RXCAL_TXIQCORR_COEF_10_B1_RXCAL_TXIQCORR_COEF_10_CHN1_LSB)
#define BB_RXCAL_TXIQCORR_COEF_10_B1_RXCAL_TXIQCORR_COEF_10_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TXIQCORR_COEF_10_B1_RXCAL_TXIQCORR_COEF_10_CHN1_LSB) & BB_RXCAL_TXIQCORR_COEF_10_B1_RXCAL_TXIQCORR_COEF_10_CHN1_MASK)
#define BB_RXCAL_TXIQCORR_COEF_10_B1_RXCAL_TXIQCORR_COEF_10_CHN1_RESET 0
#define BB_RXCAL_TXIQCORR_COEF_10_B1_ADDRESS                         0x08f8
#define BB_RXCAL_TXIQCORR_COEF_10_B1_HW_MASK                         0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_10_B1_SW_MASK                         0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_10_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TXIQCORR_COEF_10_B1_SW_WRITE_MASK                   0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_10_B1_RSTMASK                         0xffffffff
#define BB_RXCAL_TXIQCORR_COEF_10_B1_RESET                           0x00000000

// 0x08fc (BB_RXCAL_TXIQCORR_COEF_11_B1)
#define BB_RXCAL_TXIQCORR_COEF_11_B1_RXCAL_TXIQCORR_COEF_11_CHN1_MSB 17
#define BB_RXCAL_TXIQCORR_COEF_11_B1_RXCAL_TXIQCORR_COEF_11_CHN1_LSB 0
#define BB_RXCAL_TXIQCORR_COEF_11_B1_RXCAL_TXIQCORR_COEF_11_CHN1_MASK 0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_11_B1_RXCAL_TXIQCORR_COEF_11_CHN1_GET(x) (((x) & BB_RXCAL_TXIQCORR_COEF_11_B1_RXCAL_TXIQCORR_COEF_11_CHN1_MASK) >> BB_RXCAL_TXIQCORR_COEF_11_B1_RXCAL_TXIQCORR_COEF_11_CHN1_LSB)
#define BB_RXCAL_TXIQCORR_COEF_11_B1_RXCAL_TXIQCORR_COEF_11_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TXIQCORR_COEF_11_B1_RXCAL_TXIQCORR_COEF_11_CHN1_LSB) & BB_RXCAL_TXIQCORR_COEF_11_B1_RXCAL_TXIQCORR_COEF_11_CHN1_MASK)
#define BB_RXCAL_TXIQCORR_COEF_11_B1_RXCAL_TXIQCORR_COEF_11_CHN1_RESET 0
#define BB_RXCAL_TXIQCORR_COEF_11_B1_ADDRESS                         0x08fc
#define BB_RXCAL_TXIQCORR_COEF_11_B1_HW_MASK                         0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_11_B1_SW_MASK                         0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_11_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TXIQCORR_COEF_11_B1_SW_WRITE_MASK                   0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_11_B1_RSTMASK                         0xffffffff
#define BB_RXCAL_TXIQCORR_COEF_11_B1_RESET                           0x00000000

// 0x0900 (BB_RXCAL_TXIQCORR_COEF_12_B1)
#define BB_RXCAL_TXIQCORR_COEF_12_B1_RXCAL_TXIQCORR_COEF_12_CHN1_MSB 17
#define BB_RXCAL_TXIQCORR_COEF_12_B1_RXCAL_TXIQCORR_COEF_12_CHN1_LSB 0
#define BB_RXCAL_TXIQCORR_COEF_12_B1_RXCAL_TXIQCORR_COEF_12_CHN1_MASK 0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_12_B1_RXCAL_TXIQCORR_COEF_12_CHN1_GET(x) (((x) & BB_RXCAL_TXIQCORR_COEF_12_B1_RXCAL_TXIQCORR_COEF_12_CHN1_MASK) >> BB_RXCAL_TXIQCORR_COEF_12_B1_RXCAL_TXIQCORR_COEF_12_CHN1_LSB)
#define BB_RXCAL_TXIQCORR_COEF_12_B1_RXCAL_TXIQCORR_COEF_12_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TXIQCORR_COEF_12_B1_RXCAL_TXIQCORR_COEF_12_CHN1_LSB) & BB_RXCAL_TXIQCORR_COEF_12_B1_RXCAL_TXIQCORR_COEF_12_CHN1_MASK)
#define BB_RXCAL_TXIQCORR_COEF_12_B1_RXCAL_TXIQCORR_COEF_12_CHN1_RESET 0
#define BB_RXCAL_TXIQCORR_COEF_12_B1_ADDRESS                         0x0900
#define BB_RXCAL_TXIQCORR_COEF_12_B1_HW_MASK                         0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_12_B1_SW_MASK                         0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_12_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TXIQCORR_COEF_12_B1_SW_WRITE_MASK                   0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_12_B1_RSTMASK                         0xffffffff
#define BB_RXCAL_TXIQCORR_COEF_12_B1_RESET                           0x00000000

// 0x0904 (BB_RXCAL_TXIQCORR_COEF_13_B1)
#define BB_RXCAL_TXIQCORR_COEF_13_B1_RXCAL_TXIQCORR_COEF_13_CHN1_MSB 17
#define BB_RXCAL_TXIQCORR_COEF_13_B1_RXCAL_TXIQCORR_COEF_13_CHN1_LSB 0
#define BB_RXCAL_TXIQCORR_COEF_13_B1_RXCAL_TXIQCORR_COEF_13_CHN1_MASK 0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_13_B1_RXCAL_TXIQCORR_COEF_13_CHN1_GET(x) (((x) & BB_RXCAL_TXIQCORR_COEF_13_B1_RXCAL_TXIQCORR_COEF_13_CHN1_MASK) >> BB_RXCAL_TXIQCORR_COEF_13_B1_RXCAL_TXIQCORR_COEF_13_CHN1_LSB)
#define BB_RXCAL_TXIQCORR_COEF_13_B1_RXCAL_TXIQCORR_COEF_13_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TXIQCORR_COEF_13_B1_RXCAL_TXIQCORR_COEF_13_CHN1_LSB) & BB_RXCAL_TXIQCORR_COEF_13_B1_RXCAL_TXIQCORR_COEF_13_CHN1_MASK)
#define BB_RXCAL_TXIQCORR_COEF_13_B1_RXCAL_TXIQCORR_COEF_13_CHN1_RESET 0
#define BB_RXCAL_TXIQCORR_COEF_13_B1_ADDRESS                         0x0904
#define BB_RXCAL_TXIQCORR_COEF_13_B1_HW_MASK                         0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_13_B1_SW_MASK                         0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_13_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TXIQCORR_COEF_13_B1_SW_WRITE_MASK                   0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_13_B1_RSTMASK                         0xffffffff
#define BB_RXCAL_TXIQCORR_COEF_13_B1_RESET                           0x00000000

// 0x0908 (BB_RXCAL_TXIQCORR_COEF_14_B1)
#define BB_RXCAL_TXIQCORR_COEF_14_B1_RXCAL_TXIQCORR_COEF_14_CHN1_MSB 17
#define BB_RXCAL_TXIQCORR_COEF_14_B1_RXCAL_TXIQCORR_COEF_14_CHN1_LSB 0
#define BB_RXCAL_TXIQCORR_COEF_14_B1_RXCAL_TXIQCORR_COEF_14_CHN1_MASK 0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_14_B1_RXCAL_TXIQCORR_COEF_14_CHN1_GET(x) (((x) & BB_RXCAL_TXIQCORR_COEF_14_B1_RXCAL_TXIQCORR_COEF_14_CHN1_MASK) >> BB_RXCAL_TXIQCORR_COEF_14_B1_RXCAL_TXIQCORR_COEF_14_CHN1_LSB)
#define BB_RXCAL_TXIQCORR_COEF_14_B1_RXCAL_TXIQCORR_COEF_14_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TXIQCORR_COEF_14_B1_RXCAL_TXIQCORR_COEF_14_CHN1_LSB) & BB_RXCAL_TXIQCORR_COEF_14_B1_RXCAL_TXIQCORR_COEF_14_CHN1_MASK)
#define BB_RXCAL_TXIQCORR_COEF_14_B1_RXCAL_TXIQCORR_COEF_14_CHN1_RESET 0
#define BB_RXCAL_TXIQCORR_COEF_14_B1_ADDRESS                         0x0908
#define BB_RXCAL_TXIQCORR_COEF_14_B1_HW_MASK                         0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_14_B1_SW_MASK                         0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_14_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TXIQCORR_COEF_14_B1_SW_WRITE_MASK                   0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_14_B1_RSTMASK                         0xffffffff
#define BB_RXCAL_TXIQCORR_COEF_14_B1_RESET                           0x00000000

// 0x090c (BB_RXCAL_TXIQCORR_COEF_15_B1)
#define BB_RXCAL_TXIQCORR_COEF_15_B1_RXCAL_TXIQCORR_COEF_15_CHN1_MSB 17
#define BB_RXCAL_TXIQCORR_COEF_15_B1_RXCAL_TXIQCORR_COEF_15_CHN1_LSB 0
#define BB_RXCAL_TXIQCORR_COEF_15_B1_RXCAL_TXIQCORR_COEF_15_CHN1_MASK 0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_15_B1_RXCAL_TXIQCORR_COEF_15_CHN1_GET(x) (((x) & BB_RXCAL_TXIQCORR_COEF_15_B1_RXCAL_TXIQCORR_COEF_15_CHN1_MASK) >> BB_RXCAL_TXIQCORR_COEF_15_B1_RXCAL_TXIQCORR_COEF_15_CHN1_LSB)
#define BB_RXCAL_TXIQCORR_COEF_15_B1_RXCAL_TXIQCORR_COEF_15_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TXIQCORR_COEF_15_B1_RXCAL_TXIQCORR_COEF_15_CHN1_LSB) & BB_RXCAL_TXIQCORR_COEF_15_B1_RXCAL_TXIQCORR_COEF_15_CHN1_MASK)
#define BB_RXCAL_TXIQCORR_COEF_15_B1_RXCAL_TXIQCORR_COEF_15_CHN1_RESET 0
#define BB_RXCAL_TXIQCORR_COEF_15_B1_ADDRESS                         0x090c
#define BB_RXCAL_TXIQCORR_COEF_15_B1_HW_MASK                         0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_15_B1_SW_MASK                         0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_15_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TXIQCORR_COEF_15_B1_SW_WRITE_MASK                   0x0003ffff
#define BB_RXCAL_TXIQCORR_COEF_15_B1_RSTMASK                         0xffffffff
#define BB_RXCAL_TXIQCORR_COEF_15_B1_RESET                           0x00000000

// 0x0910 (BB_RXIQCORR_RXPATH_COEF_0_B1)
#define BB_RXIQCORR_RXPATH_COEF_0_B1_RXIQCORR_RXPATH_COEF_0_CHN1_MSB 17
#define BB_RXIQCORR_RXPATH_COEF_0_B1_RXIQCORR_RXPATH_COEF_0_CHN1_LSB 0
#define BB_RXIQCORR_RXPATH_COEF_0_B1_RXIQCORR_RXPATH_COEF_0_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_0_B1_RXIQCORR_RXPATH_COEF_0_CHN1_GET(x) (((x) & BB_RXIQCORR_RXPATH_COEF_0_B1_RXIQCORR_RXPATH_COEF_0_CHN1_MASK) >> BB_RXIQCORR_RXPATH_COEF_0_B1_RXIQCORR_RXPATH_COEF_0_CHN1_LSB)
#define BB_RXIQCORR_RXPATH_COEF_0_B1_RXIQCORR_RXPATH_COEF_0_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_RXPATH_COEF_0_B1_RXIQCORR_RXPATH_COEF_0_CHN1_LSB) & BB_RXIQCORR_RXPATH_COEF_0_B1_RXIQCORR_RXPATH_COEF_0_CHN1_MASK)
#define BB_RXIQCORR_RXPATH_COEF_0_B1_RXIQCORR_RXPATH_COEF_0_CHN1_RESET 0
#define BB_RXIQCORR_RXPATH_COEF_0_B1_ADDRESS                         0x0910
#define BB_RXIQCORR_RXPATH_COEF_0_B1_HW_MASK                         0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_0_B1_SW_MASK                         0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_0_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXIQCORR_RXPATH_COEF_0_B1_SW_WRITE_MASK                   0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_0_B1_RSTMASK                         0xffffffff
#define BB_RXIQCORR_RXPATH_COEF_0_B1_RESET                           0x00000000

// 0x0914 (BB_RXIQCORR_RXPATH_COEF_1_B1)
#define BB_RXIQCORR_RXPATH_COEF_1_B1_RXIQCORR_RXPATH_COEF_1_CHN1_MSB 17
#define BB_RXIQCORR_RXPATH_COEF_1_B1_RXIQCORR_RXPATH_COEF_1_CHN1_LSB 0
#define BB_RXIQCORR_RXPATH_COEF_1_B1_RXIQCORR_RXPATH_COEF_1_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_1_B1_RXIQCORR_RXPATH_COEF_1_CHN1_GET(x) (((x) & BB_RXIQCORR_RXPATH_COEF_1_B1_RXIQCORR_RXPATH_COEF_1_CHN1_MASK) >> BB_RXIQCORR_RXPATH_COEF_1_B1_RXIQCORR_RXPATH_COEF_1_CHN1_LSB)
#define BB_RXIQCORR_RXPATH_COEF_1_B1_RXIQCORR_RXPATH_COEF_1_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_RXPATH_COEF_1_B1_RXIQCORR_RXPATH_COEF_1_CHN1_LSB) & BB_RXIQCORR_RXPATH_COEF_1_B1_RXIQCORR_RXPATH_COEF_1_CHN1_MASK)
#define BB_RXIQCORR_RXPATH_COEF_1_B1_RXIQCORR_RXPATH_COEF_1_CHN1_RESET 0
#define BB_RXIQCORR_RXPATH_COEF_1_B1_ADDRESS                         0x0914
#define BB_RXIQCORR_RXPATH_COEF_1_B1_HW_MASK                         0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_1_B1_SW_MASK                         0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_1_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXIQCORR_RXPATH_COEF_1_B1_SW_WRITE_MASK                   0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_1_B1_RSTMASK                         0xffffffff
#define BB_RXIQCORR_RXPATH_COEF_1_B1_RESET                           0x00000000

// 0x0918 (BB_RXIQCORR_RXPATH_COEF_2_B1)
#define BB_RXIQCORR_RXPATH_COEF_2_B1_RXIQCORR_RXPATH_COEF_2_CHN1_MSB 17
#define BB_RXIQCORR_RXPATH_COEF_2_B1_RXIQCORR_RXPATH_COEF_2_CHN1_LSB 0
#define BB_RXIQCORR_RXPATH_COEF_2_B1_RXIQCORR_RXPATH_COEF_2_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_2_B1_RXIQCORR_RXPATH_COEF_2_CHN1_GET(x) (((x) & BB_RXIQCORR_RXPATH_COEF_2_B1_RXIQCORR_RXPATH_COEF_2_CHN1_MASK) >> BB_RXIQCORR_RXPATH_COEF_2_B1_RXIQCORR_RXPATH_COEF_2_CHN1_LSB)
#define BB_RXIQCORR_RXPATH_COEF_2_B1_RXIQCORR_RXPATH_COEF_2_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_RXPATH_COEF_2_B1_RXIQCORR_RXPATH_COEF_2_CHN1_LSB) & BB_RXIQCORR_RXPATH_COEF_2_B1_RXIQCORR_RXPATH_COEF_2_CHN1_MASK)
#define BB_RXIQCORR_RXPATH_COEF_2_B1_RXIQCORR_RXPATH_COEF_2_CHN1_RESET 0
#define BB_RXIQCORR_RXPATH_COEF_2_B1_ADDRESS                         0x0918
#define BB_RXIQCORR_RXPATH_COEF_2_B1_HW_MASK                         0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_2_B1_SW_MASK                         0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_2_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXIQCORR_RXPATH_COEF_2_B1_SW_WRITE_MASK                   0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_2_B1_RSTMASK                         0xffffffff
#define BB_RXIQCORR_RXPATH_COEF_2_B1_RESET                           0x00000000

// 0x091c (BB_RXIQCORR_RXPATH_COEF_3_B1)
#define BB_RXIQCORR_RXPATH_COEF_3_B1_RXIQCORR_RXPATH_COEF_3_CHN1_MSB 17
#define BB_RXIQCORR_RXPATH_COEF_3_B1_RXIQCORR_RXPATH_COEF_3_CHN1_LSB 0
#define BB_RXIQCORR_RXPATH_COEF_3_B1_RXIQCORR_RXPATH_COEF_3_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_3_B1_RXIQCORR_RXPATH_COEF_3_CHN1_GET(x) (((x) & BB_RXIQCORR_RXPATH_COEF_3_B1_RXIQCORR_RXPATH_COEF_3_CHN1_MASK) >> BB_RXIQCORR_RXPATH_COEF_3_B1_RXIQCORR_RXPATH_COEF_3_CHN1_LSB)
#define BB_RXIQCORR_RXPATH_COEF_3_B1_RXIQCORR_RXPATH_COEF_3_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_RXPATH_COEF_3_B1_RXIQCORR_RXPATH_COEF_3_CHN1_LSB) & BB_RXIQCORR_RXPATH_COEF_3_B1_RXIQCORR_RXPATH_COEF_3_CHN1_MASK)
#define BB_RXIQCORR_RXPATH_COEF_3_B1_RXIQCORR_RXPATH_COEF_3_CHN1_RESET 0
#define BB_RXIQCORR_RXPATH_COEF_3_B1_ADDRESS                         0x091c
#define BB_RXIQCORR_RXPATH_COEF_3_B1_HW_MASK                         0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_3_B1_SW_MASK                         0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_3_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXIQCORR_RXPATH_COEF_3_B1_SW_WRITE_MASK                   0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_3_B1_RSTMASK                         0xffffffff
#define BB_RXIQCORR_RXPATH_COEF_3_B1_RESET                           0x00000000

// 0x0920 (BB_RXIQCORR_RXPATH_COEF_4_B1)
#define BB_RXIQCORR_RXPATH_COEF_4_B1_RXIQCORR_RXPATH_COEF_4_CHN1_MSB 17
#define BB_RXIQCORR_RXPATH_COEF_4_B1_RXIQCORR_RXPATH_COEF_4_CHN1_LSB 0
#define BB_RXIQCORR_RXPATH_COEF_4_B1_RXIQCORR_RXPATH_COEF_4_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_4_B1_RXIQCORR_RXPATH_COEF_4_CHN1_GET(x) (((x) & BB_RXIQCORR_RXPATH_COEF_4_B1_RXIQCORR_RXPATH_COEF_4_CHN1_MASK) >> BB_RXIQCORR_RXPATH_COEF_4_B1_RXIQCORR_RXPATH_COEF_4_CHN1_LSB)
#define BB_RXIQCORR_RXPATH_COEF_4_B1_RXIQCORR_RXPATH_COEF_4_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_RXPATH_COEF_4_B1_RXIQCORR_RXPATH_COEF_4_CHN1_LSB) & BB_RXIQCORR_RXPATH_COEF_4_B1_RXIQCORR_RXPATH_COEF_4_CHN1_MASK)
#define BB_RXIQCORR_RXPATH_COEF_4_B1_RXIQCORR_RXPATH_COEF_4_CHN1_RESET 0
#define BB_RXIQCORR_RXPATH_COEF_4_B1_ADDRESS                         0x0920
#define BB_RXIQCORR_RXPATH_COEF_4_B1_HW_MASK                         0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_4_B1_SW_MASK                         0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_4_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXIQCORR_RXPATH_COEF_4_B1_SW_WRITE_MASK                   0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_4_B1_RSTMASK                         0xffffffff
#define BB_RXIQCORR_RXPATH_COEF_4_B1_RESET                           0x00000000

// 0x0924 (BB_RXIQCORR_RXPATH_COEF_5_B1)
#define BB_RXIQCORR_RXPATH_COEF_5_B1_RXIQCORR_RXPATH_COEF_5_CHN1_MSB 17
#define BB_RXIQCORR_RXPATH_COEF_5_B1_RXIQCORR_RXPATH_COEF_5_CHN1_LSB 0
#define BB_RXIQCORR_RXPATH_COEF_5_B1_RXIQCORR_RXPATH_COEF_5_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_5_B1_RXIQCORR_RXPATH_COEF_5_CHN1_GET(x) (((x) & BB_RXIQCORR_RXPATH_COEF_5_B1_RXIQCORR_RXPATH_COEF_5_CHN1_MASK) >> BB_RXIQCORR_RXPATH_COEF_5_B1_RXIQCORR_RXPATH_COEF_5_CHN1_LSB)
#define BB_RXIQCORR_RXPATH_COEF_5_B1_RXIQCORR_RXPATH_COEF_5_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_RXPATH_COEF_5_B1_RXIQCORR_RXPATH_COEF_5_CHN1_LSB) & BB_RXIQCORR_RXPATH_COEF_5_B1_RXIQCORR_RXPATH_COEF_5_CHN1_MASK)
#define BB_RXIQCORR_RXPATH_COEF_5_B1_RXIQCORR_RXPATH_COEF_5_CHN1_RESET 0
#define BB_RXIQCORR_RXPATH_COEF_5_B1_ADDRESS                         0x0924
#define BB_RXIQCORR_RXPATH_COEF_5_B1_HW_MASK                         0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_5_B1_SW_MASK                         0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_5_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXIQCORR_RXPATH_COEF_5_B1_SW_WRITE_MASK                   0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_5_B1_RSTMASK                         0xffffffff
#define BB_RXIQCORR_RXPATH_COEF_5_B1_RESET                           0x00000000

// 0x0928 (BB_RXIQCORR_RXPATH_COEF_6_B1)
#define BB_RXIQCORR_RXPATH_COEF_6_B1_RXIQCORR_RXPATH_COEF_6_CHN1_MSB 17
#define BB_RXIQCORR_RXPATH_COEF_6_B1_RXIQCORR_RXPATH_COEF_6_CHN1_LSB 0
#define BB_RXIQCORR_RXPATH_COEF_6_B1_RXIQCORR_RXPATH_COEF_6_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_6_B1_RXIQCORR_RXPATH_COEF_6_CHN1_GET(x) (((x) & BB_RXIQCORR_RXPATH_COEF_6_B1_RXIQCORR_RXPATH_COEF_6_CHN1_MASK) >> BB_RXIQCORR_RXPATH_COEF_6_B1_RXIQCORR_RXPATH_COEF_6_CHN1_LSB)
#define BB_RXIQCORR_RXPATH_COEF_6_B1_RXIQCORR_RXPATH_COEF_6_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_RXPATH_COEF_6_B1_RXIQCORR_RXPATH_COEF_6_CHN1_LSB) & BB_RXIQCORR_RXPATH_COEF_6_B1_RXIQCORR_RXPATH_COEF_6_CHN1_MASK)
#define BB_RXIQCORR_RXPATH_COEF_6_B1_RXIQCORR_RXPATH_COEF_6_CHN1_RESET 0
#define BB_RXIQCORR_RXPATH_COEF_6_B1_ADDRESS                         0x0928
#define BB_RXIQCORR_RXPATH_COEF_6_B1_HW_MASK                         0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_6_B1_SW_MASK                         0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_6_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXIQCORR_RXPATH_COEF_6_B1_SW_WRITE_MASK                   0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_6_B1_RSTMASK                         0xffffffff
#define BB_RXIQCORR_RXPATH_COEF_6_B1_RESET                           0x00000000

// 0x092c (BB_RXIQCORR_RXPATH_COEF_7_B1)
#define BB_RXIQCORR_RXPATH_COEF_7_B1_RXIQCORR_RXPATH_COEF_7_CHN1_MSB 17
#define BB_RXIQCORR_RXPATH_COEF_7_B1_RXIQCORR_RXPATH_COEF_7_CHN1_LSB 0
#define BB_RXIQCORR_RXPATH_COEF_7_B1_RXIQCORR_RXPATH_COEF_7_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_7_B1_RXIQCORR_RXPATH_COEF_7_CHN1_GET(x) (((x) & BB_RXIQCORR_RXPATH_COEF_7_B1_RXIQCORR_RXPATH_COEF_7_CHN1_MASK) >> BB_RXIQCORR_RXPATH_COEF_7_B1_RXIQCORR_RXPATH_COEF_7_CHN1_LSB)
#define BB_RXIQCORR_RXPATH_COEF_7_B1_RXIQCORR_RXPATH_COEF_7_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_RXPATH_COEF_7_B1_RXIQCORR_RXPATH_COEF_7_CHN1_LSB) & BB_RXIQCORR_RXPATH_COEF_7_B1_RXIQCORR_RXPATH_COEF_7_CHN1_MASK)
#define BB_RXIQCORR_RXPATH_COEF_7_B1_RXIQCORR_RXPATH_COEF_7_CHN1_RESET 0
#define BB_RXIQCORR_RXPATH_COEF_7_B1_ADDRESS                         0x092c
#define BB_RXIQCORR_RXPATH_COEF_7_B1_HW_MASK                         0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_7_B1_SW_MASK                         0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_7_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXIQCORR_RXPATH_COEF_7_B1_SW_WRITE_MASK                   0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_7_B1_RSTMASK                         0xffffffff
#define BB_RXIQCORR_RXPATH_COEF_7_B1_RESET                           0x00000000

// 0x0930 (BB_RXIQCORR_RXPATH_COEF_8_B1)
#define BB_RXIQCORR_RXPATH_COEF_8_B1_RXIQCORR_RXPATH_COEF_8_CHN1_MSB 17
#define BB_RXIQCORR_RXPATH_COEF_8_B1_RXIQCORR_RXPATH_COEF_8_CHN1_LSB 0
#define BB_RXIQCORR_RXPATH_COEF_8_B1_RXIQCORR_RXPATH_COEF_8_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_8_B1_RXIQCORR_RXPATH_COEF_8_CHN1_GET(x) (((x) & BB_RXIQCORR_RXPATH_COEF_8_B1_RXIQCORR_RXPATH_COEF_8_CHN1_MASK) >> BB_RXIQCORR_RXPATH_COEF_8_B1_RXIQCORR_RXPATH_COEF_8_CHN1_LSB)
#define BB_RXIQCORR_RXPATH_COEF_8_B1_RXIQCORR_RXPATH_COEF_8_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_RXPATH_COEF_8_B1_RXIQCORR_RXPATH_COEF_8_CHN1_LSB) & BB_RXIQCORR_RXPATH_COEF_8_B1_RXIQCORR_RXPATH_COEF_8_CHN1_MASK)
#define BB_RXIQCORR_RXPATH_COEF_8_B1_RXIQCORR_RXPATH_COEF_8_CHN1_RESET 0
#define BB_RXIQCORR_RXPATH_COEF_8_B1_ADDRESS                         0x0930
#define BB_RXIQCORR_RXPATH_COEF_8_B1_HW_MASK                         0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_8_B1_SW_MASK                         0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_8_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXIQCORR_RXPATH_COEF_8_B1_SW_WRITE_MASK                   0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_8_B1_RSTMASK                         0xffffffff
#define BB_RXIQCORR_RXPATH_COEF_8_B1_RESET                           0x00000000

// 0x0934 (BB_RXIQCORR_RXPATH_COEF_9_B1)
#define BB_RXIQCORR_RXPATH_COEF_9_B1_RXIQCORR_RXPATH_COEF_9_CHN1_MSB 17
#define BB_RXIQCORR_RXPATH_COEF_9_B1_RXIQCORR_RXPATH_COEF_9_CHN1_LSB 0
#define BB_RXIQCORR_RXPATH_COEF_9_B1_RXIQCORR_RXPATH_COEF_9_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_9_B1_RXIQCORR_RXPATH_COEF_9_CHN1_GET(x) (((x) & BB_RXIQCORR_RXPATH_COEF_9_B1_RXIQCORR_RXPATH_COEF_9_CHN1_MASK) >> BB_RXIQCORR_RXPATH_COEF_9_B1_RXIQCORR_RXPATH_COEF_9_CHN1_LSB)
#define BB_RXIQCORR_RXPATH_COEF_9_B1_RXIQCORR_RXPATH_COEF_9_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_RXPATH_COEF_9_B1_RXIQCORR_RXPATH_COEF_9_CHN1_LSB) & BB_RXIQCORR_RXPATH_COEF_9_B1_RXIQCORR_RXPATH_COEF_9_CHN1_MASK)
#define BB_RXIQCORR_RXPATH_COEF_9_B1_RXIQCORR_RXPATH_COEF_9_CHN1_RESET 0
#define BB_RXIQCORR_RXPATH_COEF_9_B1_ADDRESS                         0x0934
#define BB_RXIQCORR_RXPATH_COEF_9_B1_HW_MASK                         0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_9_B1_SW_MASK                         0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_9_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXIQCORR_RXPATH_COEF_9_B1_SW_WRITE_MASK                   0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_9_B1_RSTMASK                         0xffffffff
#define BB_RXIQCORR_RXPATH_COEF_9_B1_RESET                           0x00000000

// 0x0938 (BB_RXIQCORR_RXPATH_COEF_10_B1)
#define BB_RXIQCORR_RXPATH_COEF_10_B1_RXIQCORR_RXPATH_COEF_10_CHN1_MSB 17
#define BB_RXIQCORR_RXPATH_COEF_10_B1_RXIQCORR_RXPATH_COEF_10_CHN1_LSB 0
#define BB_RXIQCORR_RXPATH_COEF_10_B1_RXIQCORR_RXPATH_COEF_10_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_10_B1_RXIQCORR_RXPATH_COEF_10_CHN1_GET(x) (((x) & BB_RXIQCORR_RXPATH_COEF_10_B1_RXIQCORR_RXPATH_COEF_10_CHN1_MASK) >> BB_RXIQCORR_RXPATH_COEF_10_B1_RXIQCORR_RXPATH_COEF_10_CHN1_LSB)
#define BB_RXIQCORR_RXPATH_COEF_10_B1_RXIQCORR_RXPATH_COEF_10_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_RXPATH_COEF_10_B1_RXIQCORR_RXPATH_COEF_10_CHN1_LSB) & BB_RXIQCORR_RXPATH_COEF_10_B1_RXIQCORR_RXPATH_COEF_10_CHN1_MASK)
#define BB_RXIQCORR_RXPATH_COEF_10_B1_RXIQCORR_RXPATH_COEF_10_CHN1_RESET 0
#define BB_RXIQCORR_RXPATH_COEF_10_B1_ADDRESS                        0x0938
#define BB_RXIQCORR_RXPATH_COEF_10_B1_HW_MASK                        0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_10_B1_SW_MASK                        0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_10_B1_HW_WRITE_MASK                  0x00000000
#define BB_RXIQCORR_RXPATH_COEF_10_B1_SW_WRITE_MASK                  0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_10_B1_RSTMASK                        0xffffffff
#define BB_RXIQCORR_RXPATH_COEF_10_B1_RESET                          0x00000000

// 0x093c (BB_RXIQCORR_RXPATH_COEF_11_B1)
#define BB_RXIQCORR_RXPATH_COEF_11_B1_RXIQCORR_RXPATH_COEF_11_CHN1_MSB 17
#define BB_RXIQCORR_RXPATH_COEF_11_B1_RXIQCORR_RXPATH_COEF_11_CHN1_LSB 0
#define BB_RXIQCORR_RXPATH_COEF_11_B1_RXIQCORR_RXPATH_COEF_11_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_11_B1_RXIQCORR_RXPATH_COEF_11_CHN1_GET(x) (((x) & BB_RXIQCORR_RXPATH_COEF_11_B1_RXIQCORR_RXPATH_COEF_11_CHN1_MASK) >> BB_RXIQCORR_RXPATH_COEF_11_B1_RXIQCORR_RXPATH_COEF_11_CHN1_LSB)
#define BB_RXIQCORR_RXPATH_COEF_11_B1_RXIQCORR_RXPATH_COEF_11_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_RXPATH_COEF_11_B1_RXIQCORR_RXPATH_COEF_11_CHN1_LSB) & BB_RXIQCORR_RXPATH_COEF_11_B1_RXIQCORR_RXPATH_COEF_11_CHN1_MASK)
#define BB_RXIQCORR_RXPATH_COEF_11_B1_RXIQCORR_RXPATH_COEF_11_CHN1_RESET 0
#define BB_RXIQCORR_RXPATH_COEF_11_B1_ADDRESS                        0x093c
#define BB_RXIQCORR_RXPATH_COEF_11_B1_HW_MASK                        0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_11_B1_SW_MASK                        0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_11_B1_HW_WRITE_MASK                  0x00000000
#define BB_RXIQCORR_RXPATH_COEF_11_B1_SW_WRITE_MASK                  0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_11_B1_RSTMASK                        0xffffffff
#define BB_RXIQCORR_RXPATH_COEF_11_B1_RESET                          0x00000000

// 0x0940 (BB_RXIQCORR_RXPATH_COEF_12_B1)
#define BB_RXIQCORR_RXPATH_COEF_12_B1_RXIQCORR_RXPATH_COEF_12_CHN1_MSB 17
#define BB_RXIQCORR_RXPATH_COEF_12_B1_RXIQCORR_RXPATH_COEF_12_CHN1_LSB 0
#define BB_RXIQCORR_RXPATH_COEF_12_B1_RXIQCORR_RXPATH_COEF_12_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_12_B1_RXIQCORR_RXPATH_COEF_12_CHN1_GET(x) (((x) & BB_RXIQCORR_RXPATH_COEF_12_B1_RXIQCORR_RXPATH_COEF_12_CHN1_MASK) >> BB_RXIQCORR_RXPATH_COEF_12_B1_RXIQCORR_RXPATH_COEF_12_CHN1_LSB)
#define BB_RXIQCORR_RXPATH_COEF_12_B1_RXIQCORR_RXPATH_COEF_12_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_RXPATH_COEF_12_B1_RXIQCORR_RXPATH_COEF_12_CHN1_LSB) & BB_RXIQCORR_RXPATH_COEF_12_B1_RXIQCORR_RXPATH_COEF_12_CHN1_MASK)
#define BB_RXIQCORR_RXPATH_COEF_12_B1_RXIQCORR_RXPATH_COEF_12_CHN1_RESET 0
#define BB_RXIQCORR_RXPATH_COEF_12_B1_ADDRESS                        0x0940
#define BB_RXIQCORR_RXPATH_COEF_12_B1_HW_MASK                        0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_12_B1_SW_MASK                        0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_12_B1_HW_WRITE_MASK                  0x00000000
#define BB_RXIQCORR_RXPATH_COEF_12_B1_SW_WRITE_MASK                  0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_12_B1_RSTMASK                        0xffffffff
#define BB_RXIQCORR_RXPATH_COEF_12_B1_RESET                          0x00000000

// 0x0944 (BB_RXIQCORR_RXPATH_COEF_13_B1)
#define BB_RXIQCORR_RXPATH_COEF_13_B1_RXIQCORR_RXPATH_COEF_13_CHN1_MSB 17
#define BB_RXIQCORR_RXPATH_COEF_13_B1_RXIQCORR_RXPATH_COEF_13_CHN1_LSB 0
#define BB_RXIQCORR_RXPATH_COEF_13_B1_RXIQCORR_RXPATH_COEF_13_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_13_B1_RXIQCORR_RXPATH_COEF_13_CHN1_GET(x) (((x) & BB_RXIQCORR_RXPATH_COEF_13_B1_RXIQCORR_RXPATH_COEF_13_CHN1_MASK) >> BB_RXIQCORR_RXPATH_COEF_13_B1_RXIQCORR_RXPATH_COEF_13_CHN1_LSB)
#define BB_RXIQCORR_RXPATH_COEF_13_B1_RXIQCORR_RXPATH_COEF_13_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_RXPATH_COEF_13_B1_RXIQCORR_RXPATH_COEF_13_CHN1_LSB) & BB_RXIQCORR_RXPATH_COEF_13_B1_RXIQCORR_RXPATH_COEF_13_CHN1_MASK)
#define BB_RXIQCORR_RXPATH_COEF_13_B1_RXIQCORR_RXPATH_COEF_13_CHN1_RESET 0
#define BB_RXIQCORR_RXPATH_COEF_13_B1_ADDRESS                        0x0944
#define BB_RXIQCORR_RXPATH_COEF_13_B1_HW_MASK                        0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_13_B1_SW_MASK                        0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_13_B1_HW_WRITE_MASK                  0x00000000
#define BB_RXIQCORR_RXPATH_COEF_13_B1_SW_WRITE_MASK                  0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_13_B1_RSTMASK                        0xffffffff
#define BB_RXIQCORR_RXPATH_COEF_13_B1_RESET                          0x00000000

// 0x0948 (BB_RXIQCORR_RXPATH_COEF_14_B1)
#define BB_RXIQCORR_RXPATH_COEF_14_B1_RXIQCORR_RXPATH_COEF_14_CHN1_MSB 17
#define BB_RXIQCORR_RXPATH_COEF_14_B1_RXIQCORR_RXPATH_COEF_14_CHN1_LSB 0
#define BB_RXIQCORR_RXPATH_COEF_14_B1_RXIQCORR_RXPATH_COEF_14_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_14_B1_RXIQCORR_RXPATH_COEF_14_CHN1_GET(x) (((x) & BB_RXIQCORR_RXPATH_COEF_14_B1_RXIQCORR_RXPATH_COEF_14_CHN1_MASK) >> BB_RXIQCORR_RXPATH_COEF_14_B1_RXIQCORR_RXPATH_COEF_14_CHN1_LSB)
#define BB_RXIQCORR_RXPATH_COEF_14_B1_RXIQCORR_RXPATH_COEF_14_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_RXPATH_COEF_14_B1_RXIQCORR_RXPATH_COEF_14_CHN1_LSB) & BB_RXIQCORR_RXPATH_COEF_14_B1_RXIQCORR_RXPATH_COEF_14_CHN1_MASK)
#define BB_RXIQCORR_RXPATH_COEF_14_B1_RXIQCORR_RXPATH_COEF_14_CHN1_RESET 0
#define BB_RXIQCORR_RXPATH_COEF_14_B1_ADDRESS                        0x0948
#define BB_RXIQCORR_RXPATH_COEF_14_B1_HW_MASK                        0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_14_B1_SW_MASK                        0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_14_B1_HW_WRITE_MASK                  0x00000000
#define BB_RXIQCORR_RXPATH_COEF_14_B1_SW_WRITE_MASK                  0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_14_B1_RSTMASK                        0xffffffff
#define BB_RXIQCORR_RXPATH_COEF_14_B1_RESET                          0x00000000

// 0x094c (BB_RXIQCORR_RXPATH_COEF_15_B1)
#define BB_RXIQCORR_RXPATH_COEF_15_B1_RXIQCORR_RXPATH_COEF_15_CHN1_MSB 17
#define BB_RXIQCORR_RXPATH_COEF_15_B1_RXIQCORR_RXPATH_COEF_15_CHN1_LSB 0
#define BB_RXIQCORR_RXPATH_COEF_15_B1_RXIQCORR_RXPATH_COEF_15_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_15_B1_RXIQCORR_RXPATH_COEF_15_CHN1_GET(x) (((x) & BB_RXIQCORR_RXPATH_COEF_15_B1_RXIQCORR_RXPATH_COEF_15_CHN1_MASK) >> BB_RXIQCORR_RXPATH_COEF_15_B1_RXIQCORR_RXPATH_COEF_15_CHN1_LSB)
#define BB_RXIQCORR_RXPATH_COEF_15_B1_RXIQCORR_RXPATH_COEF_15_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_RXPATH_COEF_15_B1_RXIQCORR_RXPATH_COEF_15_CHN1_LSB) & BB_RXIQCORR_RXPATH_COEF_15_B1_RXIQCORR_RXPATH_COEF_15_CHN1_MASK)
#define BB_RXIQCORR_RXPATH_COEF_15_B1_RXIQCORR_RXPATH_COEF_15_CHN1_RESET 0
#define BB_RXIQCORR_RXPATH_COEF_15_B1_ADDRESS                        0x094c
#define BB_RXIQCORR_RXPATH_COEF_15_B1_HW_MASK                        0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_15_B1_SW_MASK                        0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_15_B1_HW_WRITE_MASK                  0x00000000
#define BB_RXIQCORR_RXPATH_COEF_15_B1_SW_WRITE_MASK                  0x0003ffff
#define BB_RXIQCORR_RXPATH_COEF_15_B1_RSTMASK                        0xffffffff
#define BB_RXIQCORR_RXPATH_COEF_15_B1_RESET                          0x00000000

// 0x0950 (BB_RXIQCORR_TXPATH_COEF_0_B1)
#define BB_RXIQCORR_TXPATH_COEF_0_B1_RXIQCORR_TXPATH_COEF_0_CHN1_MSB 17
#define BB_RXIQCORR_TXPATH_COEF_0_B1_RXIQCORR_TXPATH_COEF_0_CHN1_LSB 0
#define BB_RXIQCORR_TXPATH_COEF_0_B1_RXIQCORR_TXPATH_COEF_0_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_0_B1_RXIQCORR_TXPATH_COEF_0_CHN1_GET(x) (((x) & BB_RXIQCORR_TXPATH_COEF_0_B1_RXIQCORR_TXPATH_COEF_0_CHN1_MASK) >> BB_RXIQCORR_TXPATH_COEF_0_B1_RXIQCORR_TXPATH_COEF_0_CHN1_LSB)
#define BB_RXIQCORR_TXPATH_COEF_0_B1_RXIQCORR_TXPATH_COEF_0_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_TXPATH_COEF_0_B1_RXIQCORR_TXPATH_COEF_0_CHN1_LSB) & BB_RXIQCORR_TXPATH_COEF_0_B1_RXIQCORR_TXPATH_COEF_0_CHN1_MASK)
#define BB_RXIQCORR_TXPATH_COEF_0_B1_RXIQCORR_TXPATH_COEF_0_CHN1_RESET 0
#define BB_RXIQCORR_TXPATH_COEF_0_B1_ADDRESS                         0x0950
#define BB_RXIQCORR_TXPATH_COEF_0_B1_HW_MASK                         0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_0_B1_SW_MASK                         0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_0_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXIQCORR_TXPATH_COEF_0_B1_SW_WRITE_MASK                   0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_0_B1_RSTMASK                         0xffffffff
#define BB_RXIQCORR_TXPATH_COEF_0_B1_RESET                           0x00000000

// 0x0954 (BB_RXIQCORR_TXPATH_COEF_1_B1)
#define BB_RXIQCORR_TXPATH_COEF_1_B1_RXIQCORR_TXPATH_COEF_1_CHN1_MSB 17
#define BB_RXIQCORR_TXPATH_COEF_1_B1_RXIQCORR_TXPATH_COEF_1_CHN1_LSB 0
#define BB_RXIQCORR_TXPATH_COEF_1_B1_RXIQCORR_TXPATH_COEF_1_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_1_B1_RXIQCORR_TXPATH_COEF_1_CHN1_GET(x) (((x) & BB_RXIQCORR_TXPATH_COEF_1_B1_RXIQCORR_TXPATH_COEF_1_CHN1_MASK) >> BB_RXIQCORR_TXPATH_COEF_1_B1_RXIQCORR_TXPATH_COEF_1_CHN1_LSB)
#define BB_RXIQCORR_TXPATH_COEF_1_B1_RXIQCORR_TXPATH_COEF_1_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_TXPATH_COEF_1_B1_RXIQCORR_TXPATH_COEF_1_CHN1_LSB) & BB_RXIQCORR_TXPATH_COEF_1_B1_RXIQCORR_TXPATH_COEF_1_CHN1_MASK)
#define BB_RXIQCORR_TXPATH_COEF_1_B1_RXIQCORR_TXPATH_COEF_1_CHN1_RESET 0
#define BB_RXIQCORR_TXPATH_COEF_1_B1_ADDRESS                         0x0954
#define BB_RXIQCORR_TXPATH_COEF_1_B1_HW_MASK                         0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_1_B1_SW_MASK                         0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_1_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXIQCORR_TXPATH_COEF_1_B1_SW_WRITE_MASK                   0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_1_B1_RSTMASK                         0xffffffff
#define BB_RXIQCORR_TXPATH_COEF_1_B1_RESET                           0x00000000

// 0x0958 (BB_RXIQCORR_TXPATH_COEF_2_B1)
#define BB_RXIQCORR_TXPATH_COEF_2_B1_RXIQCORR_TXPATH_COEF_2_CHN1_MSB 17
#define BB_RXIQCORR_TXPATH_COEF_2_B1_RXIQCORR_TXPATH_COEF_2_CHN1_LSB 0
#define BB_RXIQCORR_TXPATH_COEF_2_B1_RXIQCORR_TXPATH_COEF_2_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_2_B1_RXIQCORR_TXPATH_COEF_2_CHN1_GET(x) (((x) & BB_RXIQCORR_TXPATH_COEF_2_B1_RXIQCORR_TXPATH_COEF_2_CHN1_MASK) >> BB_RXIQCORR_TXPATH_COEF_2_B1_RXIQCORR_TXPATH_COEF_2_CHN1_LSB)
#define BB_RXIQCORR_TXPATH_COEF_2_B1_RXIQCORR_TXPATH_COEF_2_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_TXPATH_COEF_2_B1_RXIQCORR_TXPATH_COEF_2_CHN1_LSB) & BB_RXIQCORR_TXPATH_COEF_2_B1_RXIQCORR_TXPATH_COEF_2_CHN1_MASK)
#define BB_RXIQCORR_TXPATH_COEF_2_B1_RXIQCORR_TXPATH_COEF_2_CHN1_RESET 0
#define BB_RXIQCORR_TXPATH_COEF_2_B1_ADDRESS                         0x0958
#define BB_RXIQCORR_TXPATH_COEF_2_B1_HW_MASK                         0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_2_B1_SW_MASK                         0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_2_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXIQCORR_TXPATH_COEF_2_B1_SW_WRITE_MASK                   0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_2_B1_RSTMASK                         0xffffffff
#define BB_RXIQCORR_TXPATH_COEF_2_B1_RESET                           0x00000000

// 0x095c (BB_RXIQCORR_TXPATH_COEF_3_B1)
#define BB_RXIQCORR_TXPATH_COEF_3_B1_RXIQCORR_TXPATH_COEF_3_CHN1_MSB 17
#define BB_RXIQCORR_TXPATH_COEF_3_B1_RXIQCORR_TXPATH_COEF_3_CHN1_LSB 0
#define BB_RXIQCORR_TXPATH_COEF_3_B1_RXIQCORR_TXPATH_COEF_3_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_3_B1_RXIQCORR_TXPATH_COEF_3_CHN1_GET(x) (((x) & BB_RXIQCORR_TXPATH_COEF_3_B1_RXIQCORR_TXPATH_COEF_3_CHN1_MASK) >> BB_RXIQCORR_TXPATH_COEF_3_B1_RXIQCORR_TXPATH_COEF_3_CHN1_LSB)
#define BB_RXIQCORR_TXPATH_COEF_3_B1_RXIQCORR_TXPATH_COEF_3_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_TXPATH_COEF_3_B1_RXIQCORR_TXPATH_COEF_3_CHN1_LSB) & BB_RXIQCORR_TXPATH_COEF_3_B1_RXIQCORR_TXPATH_COEF_3_CHN1_MASK)
#define BB_RXIQCORR_TXPATH_COEF_3_B1_RXIQCORR_TXPATH_COEF_3_CHN1_RESET 0
#define BB_RXIQCORR_TXPATH_COEF_3_B1_ADDRESS                         0x095c
#define BB_RXIQCORR_TXPATH_COEF_3_B1_HW_MASK                         0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_3_B1_SW_MASK                         0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_3_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXIQCORR_TXPATH_COEF_3_B1_SW_WRITE_MASK                   0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_3_B1_RSTMASK                         0xffffffff
#define BB_RXIQCORR_TXPATH_COEF_3_B1_RESET                           0x00000000

// 0x0960 (BB_RXIQCORR_TXPATH_COEF_4_B1)
#define BB_RXIQCORR_TXPATH_COEF_4_B1_RXIQCORR_TXPATH_COEF_4_CHN1_MSB 17
#define BB_RXIQCORR_TXPATH_COEF_4_B1_RXIQCORR_TXPATH_COEF_4_CHN1_LSB 0
#define BB_RXIQCORR_TXPATH_COEF_4_B1_RXIQCORR_TXPATH_COEF_4_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_4_B1_RXIQCORR_TXPATH_COEF_4_CHN1_GET(x) (((x) & BB_RXIQCORR_TXPATH_COEF_4_B1_RXIQCORR_TXPATH_COEF_4_CHN1_MASK) >> BB_RXIQCORR_TXPATH_COEF_4_B1_RXIQCORR_TXPATH_COEF_4_CHN1_LSB)
#define BB_RXIQCORR_TXPATH_COEF_4_B1_RXIQCORR_TXPATH_COEF_4_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_TXPATH_COEF_4_B1_RXIQCORR_TXPATH_COEF_4_CHN1_LSB) & BB_RXIQCORR_TXPATH_COEF_4_B1_RXIQCORR_TXPATH_COEF_4_CHN1_MASK)
#define BB_RXIQCORR_TXPATH_COEF_4_B1_RXIQCORR_TXPATH_COEF_4_CHN1_RESET 0
#define BB_RXIQCORR_TXPATH_COEF_4_B1_ADDRESS                         0x0960
#define BB_RXIQCORR_TXPATH_COEF_4_B1_HW_MASK                         0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_4_B1_SW_MASK                         0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_4_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXIQCORR_TXPATH_COEF_4_B1_SW_WRITE_MASK                   0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_4_B1_RSTMASK                         0xffffffff
#define BB_RXIQCORR_TXPATH_COEF_4_B1_RESET                           0x00000000

// 0x0964 (BB_RXIQCORR_TXPATH_COEF_5_B1)
#define BB_RXIQCORR_TXPATH_COEF_5_B1_RXIQCORR_TXPATH_COEF_5_CHN1_MSB 17
#define BB_RXIQCORR_TXPATH_COEF_5_B1_RXIQCORR_TXPATH_COEF_5_CHN1_LSB 0
#define BB_RXIQCORR_TXPATH_COEF_5_B1_RXIQCORR_TXPATH_COEF_5_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_5_B1_RXIQCORR_TXPATH_COEF_5_CHN1_GET(x) (((x) & BB_RXIQCORR_TXPATH_COEF_5_B1_RXIQCORR_TXPATH_COEF_5_CHN1_MASK) >> BB_RXIQCORR_TXPATH_COEF_5_B1_RXIQCORR_TXPATH_COEF_5_CHN1_LSB)
#define BB_RXIQCORR_TXPATH_COEF_5_B1_RXIQCORR_TXPATH_COEF_5_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_TXPATH_COEF_5_B1_RXIQCORR_TXPATH_COEF_5_CHN1_LSB) & BB_RXIQCORR_TXPATH_COEF_5_B1_RXIQCORR_TXPATH_COEF_5_CHN1_MASK)
#define BB_RXIQCORR_TXPATH_COEF_5_B1_RXIQCORR_TXPATH_COEF_5_CHN1_RESET 0
#define BB_RXIQCORR_TXPATH_COEF_5_B1_ADDRESS                         0x0964
#define BB_RXIQCORR_TXPATH_COEF_5_B1_HW_MASK                         0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_5_B1_SW_MASK                         0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_5_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXIQCORR_TXPATH_COEF_5_B1_SW_WRITE_MASK                   0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_5_B1_RSTMASK                         0xffffffff
#define BB_RXIQCORR_TXPATH_COEF_5_B1_RESET                           0x00000000

// 0x0968 (BB_RXIQCORR_TXPATH_COEF_6_B1)
#define BB_RXIQCORR_TXPATH_COEF_6_B1_RXIQCORR_TXPATH_COEF_6_CHN1_MSB 17
#define BB_RXIQCORR_TXPATH_COEF_6_B1_RXIQCORR_TXPATH_COEF_6_CHN1_LSB 0
#define BB_RXIQCORR_TXPATH_COEF_6_B1_RXIQCORR_TXPATH_COEF_6_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_6_B1_RXIQCORR_TXPATH_COEF_6_CHN1_GET(x) (((x) & BB_RXIQCORR_TXPATH_COEF_6_B1_RXIQCORR_TXPATH_COEF_6_CHN1_MASK) >> BB_RXIQCORR_TXPATH_COEF_6_B1_RXIQCORR_TXPATH_COEF_6_CHN1_LSB)
#define BB_RXIQCORR_TXPATH_COEF_6_B1_RXIQCORR_TXPATH_COEF_6_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_TXPATH_COEF_6_B1_RXIQCORR_TXPATH_COEF_6_CHN1_LSB) & BB_RXIQCORR_TXPATH_COEF_6_B1_RXIQCORR_TXPATH_COEF_6_CHN1_MASK)
#define BB_RXIQCORR_TXPATH_COEF_6_B1_RXIQCORR_TXPATH_COEF_6_CHN1_RESET 0
#define BB_RXIQCORR_TXPATH_COEF_6_B1_ADDRESS                         0x0968
#define BB_RXIQCORR_TXPATH_COEF_6_B1_HW_MASK                         0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_6_B1_SW_MASK                         0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_6_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXIQCORR_TXPATH_COEF_6_B1_SW_WRITE_MASK                   0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_6_B1_RSTMASK                         0xffffffff
#define BB_RXIQCORR_TXPATH_COEF_6_B1_RESET                           0x00000000

// 0x096c (BB_RXIQCORR_TXPATH_COEF_7_B1)
#define BB_RXIQCORR_TXPATH_COEF_7_B1_RXIQCORR_TXPATH_COEF_7_CHN1_MSB 17
#define BB_RXIQCORR_TXPATH_COEF_7_B1_RXIQCORR_TXPATH_COEF_7_CHN1_LSB 0
#define BB_RXIQCORR_TXPATH_COEF_7_B1_RXIQCORR_TXPATH_COEF_7_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_7_B1_RXIQCORR_TXPATH_COEF_7_CHN1_GET(x) (((x) & BB_RXIQCORR_TXPATH_COEF_7_B1_RXIQCORR_TXPATH_COEF_7_CHN1_MASK) >> BB_RXIQCORR_TXPATH_COEF_7_B1_RXIQCORR_TXPATH_COEF_7_CHN1_LSB)
#define BB_RXIQCORR_TXPATH_COEF_7_B1_RXIQCORR_TXPATH_COEF_7_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_TXPATH_COEF_7_B1_RXIQCORR_TXPATH_COEF_7_CHN1_LSB) & BB_RXIQCORR_TXPATH_COEF_7_B1_RXIQCORR_TXPATH_COEF_7_CHN1_MASK)
#define BB_RXIQCORR_TXPATH_COEF_7_B1_RXIQCORR_TXPATH_COEF_7_CHN1_RESET 0
#define BB_RXIQCORR_TXPATH_COEF_7_B1_ADDRESS                         0x096c
#define BB_RXIQCORR_TXPATH_COEF_7_B1_HW_MASK                         0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_7_B1_SW_MASK                         0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_7_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXIQCORR_TXPATH_COEF_7_B1_SW_WRITE_MASK                   0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_7_B1_RSTMASK                         0xffffffff
#define BB_RXIQCORR_TXPATH_COEF_7_B1_RESET                           0x00000000

// 0x0970 (BB_RXIQCORR_TXPATH_COEF_8_B1)
#define BB_RXIQCORR_TXPATH_COEF_8_B1_RXIQCORR_TXPATH_COEF_8_CHN1_MSB 17
#define BB_RXIQCORR_TXPATH_COEF_8_B1_RXIQCORR_TXPATH_COEF_8_CHN1_LSB 0
#define BB_RXIQCORR_TXPATH_COEF_8_B1_RXIQCORR_TXPATH_COEF_8_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_8_B1_RXIQCORR_TXPATH_COEF_8_CHN1_GET(x) (((x) & BB_RXIQCORR_TXPATH_COEF_8_B1_RXIQCORR_TXPATH_COEF_8_CHN1_MASK) >> BB_RXIQCORR_TXPATH_COEF_8_B1_RXIQCORR_TXPATH_COEF_8_CHN1_LSB)
#define BB_RXIQCORR_TXPATH_COEF_8_B1_RXIQCORR_TXPATH_COEF_8_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_TXPATH_COEF_8_B1_RXIQCORR_TXPATH_COEF_8_CHN1_LSB) & BB_RXIQCORR_TXPATH_COEF_8_B1_RXIQCORR_TXPATH_COEF_8_CHN1_MASK)
#define BB_RXIQCORR_TXPATH_COEF_8_B1_RXIQCORR_TXPATH_COEF_8_CHN1_RESET 0
#define BB_RXIQCORR_TXPATH_COEF_8_B1_ADDRESS                         0x0970
#define BB_RXIQCORR_TXPATH_COEF_8_B1_HW_MASK                         0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_8_B1_SW_MASK                         0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_8_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXIQCORR_TXPATH_COEF_8_B1_SW_WRITE_MASK                   0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_8_B1_RSTMASK                         0xffffffff
#define BB_RXIQCORR_TXPATH_COEF_8_B1_RESET                           0x00000000

// 0x0974 (BB_RXIQCORR_TXPATH_COEF_9_B1)
#define BB_RXIQCORR_TXPATH_COEF_9_B1_RXIQCORR_TXPATH_COEF_9_CHN1_MSB 17
#define BB_RXIQCORR_TXPATH_COEF_9_B1_RXIQCORR_TXPATH_COEF_9_CHN1_LSB 0
#define BB_RXIQCORR_TXPATH_COEF_9_B1_RXIQCORR_TXPATH_COEF_9_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_9_B1_RXIQCORR_TXPATH_COEF_9_CHN1_GET(x) (((x) & BB_RXIQCORR_TXPATH_COEF_9_B1_RXIQCORR_TXPATH_COEF_9_CHN1_MASK) >> BB_RXIQCORR_TXPATH_COEF_9_B1_RXIQCORR_TXPATH_COEF_9_CHN1_LSB)
#define BB_RXIQCORR_TXPATH_COEF_9_B1_RXIQCORR_TXPATH_COEF_9_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_TXPATH_COEF_9_B1_RXIQCORR_TXPATH_COEF_9_CHN1_LSB) & BB_RXIQCORR_TXPATH_COEF_9_B1_RXIQCORR_TXPATH_COEF_9_CHN1_MASK)
#define BB_RXIQCORR_TXPATH_COEF_9_B1_RXIQCORR_TXPATH_COEF_9_CHN1_RESET 0
#define BB_RXIQCORR_TXPATH_COEF_9_B1_ADDRESS                         0x0974
#define BB_RXIQCORR_TXPATH_COEF_9_B1_HW_MASK                         0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_9_B1_SW_MASK                         0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_9_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXIQCORR_TXPATH_COEF_9_B1_SW_WRITE_MASK                   0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_9_B1_RSTMASK                         0xffffffff
#define BB_RXIQCORR_TXPATH_COEF_9_B1_RESET                           0x00000000

// 0x0978 (BB_RXIQCORR_TXPATH_COEF_10_B1)
#define BB_RXIQCORR_TXPATH_COEF_10_B1_RXIQCORR_TXPATH_COEF_10_CHN1_MSB 17
#define BB_RXIQCORR_TXPATH_COEF_10_B1_RXIQCORR_TXPATH_COEF_10_CHN1_LSB 0
#define BB_RXIQCORR_TXPATH_COEF_10_B1_RXIQCORR_TXPATH_COEF_10_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_10_B1_RXIQCORR_TXPATH_COEF_10_CHN1_GET(x) (((x) & BB_RXIQCORR_TXPATH_COEF_10_B1_RXIQCORR_TXPATH_COEF_10_CHN1_MASK) >> BB_RXIQCORR_TXPATH_COEF_10_B1_RXIQCORR_TXPATH_COEF_10_CHN1_LSB)
#define BB_RXIQCORR_TXPATH_COEF_10_B1_RXIQCORR_TXPATH_COEF_10_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_TXPATH_COEF_10_B1_RXIQCORR_TXPATH_COEF_10_CHN1_LSB) & BB_RXIQCORR_TXPATH_COEF_10_B1_RXIQCORR_TXPATH_COEF_10_CHN1_MASK)
#define BB_RXIQCORR_TXPATH_COEF_10_B1_RXIQCORR_TXPATH_COEF_10_CHN1_RESET 0
#define BB_RXIQCORR_TXPATH_COEF_10_B1_ADDRESS                        0x0978
#define BB_RXIQCORR_TXPATH_COEF_10_B1_HW_MASK                        0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_10_B1_SW_MASK                        0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_10_B1_HW_WRITE_MASK                  0x00000000
#define BB_RXIQCORR_TXPATH_COEF_10_B1_SW_WRITE_MASK                  0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_10_B1_RSTMASK                        0xffffffff
#define BB_RXIQCORR_TXPATH_COEF_10_B1_RESET                          0x00000000

// 0x097c (BB_RXIQCORR_TXPATH_COEF_11_B1)
#define BB_RXIQCORR_TXPATH_COEF_11_B1_RXIQCORR_TXPATH_COEF_11_CHN1_MSB 17
#define BB_RXIQCORR_TXPATH_COEF_11_B1_RXIQCORR_TXPATH_COEF_11_CHN1_LSB 0
#define BB_RXIQCORR_TXPATH_COEF_11_B1_RXIQCORR_TXPATH_COEF_11_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_11_B1_RXIQCORR_TXPATH_COEF_11_CHN1_GET(x) (((x) & BB_RXIQCORR_TXPATH_COEF_11_B1_RXIQCORR_TXPATH_COEF_11_CHN1_MASK) >> BB_RXIQCORR_TXPATH_COEF_11_B1_RXIQCORR_TXPATH_COEF_11_CHN1_LSB)
#define BB_RXIQCORR_TXPATH_COEF_11_B1_RXIQCORR_TXPATH_COEF_11_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_TXPATH_COEF_11_B1_RXIQCORR_TXPATH_COEF_11_CHN1_LSB) & BB_RXIQCORR_TXPATH_COEF_11_B1_RXIQCORR_TXPATH_COEF_11_CHN1_MASK)
#define BB_RXIQCORR_TXPATH_COEF_11_B1_RXIQCORR_TXPATH_COEF_11_CHN1_RESET 0
#define BB_RXIQCORR_TXPATH_COEF_11_B1_ADDRESS                        0x097c
#define BB_RXIQCORR_TXPATH_COEF_11_B1_HW_MASK                        0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_11_B1_SW_MASK                        0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_11_B1_HW_WRITE_MASK                  0x00000000
#define BB_RXIQCORR_TXPATH_COEF_11_B1_SW_WRITE_MASK                  0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_11_B1_RSTMASK                        0xffffffff
#define BB_RXIQCORR_TXPATH_COEF_11_B1_RESET                          0x00000000

// 0x0980 (BB_RXIQCORR_TXPATH_COEF_12_B1)
#define BB_RXIQCORR_TXPATH_COEF_12_B1_RXIQCORR_TXPATH_COEF_12_CHN1_MSB 17
#define BB_RXIQCORR_TXPATH_COEF_12_B1_RXIQCORR_TXPATH_COEF_12_CHN1_LSB 0
#define BB_RXIQCORR_TXPATH_COEF_12_B1_RXIQCORR_TXPATH_COEF_12_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_12_B1_RXIQCORR_TXPATH_COEF_12_CHN1_GET(x) (((x) & BB_RXIQCORR_TXPATH_COEF_12_B1_RXIQCORR_TXPATH_COEF_12_CHN1_MASK) >> BB_RXIQCORR_TXPATH_COEF_12_B1_RXIQCORR_TXPATH_COEF_12_CHN1_LSB)
#define BB_RXIQCORR_TXPATH_COEF_12_B1_RXIQCORR_TXPATH_COEF_12_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_TXPATH_COEF_12_B1_RXIQCORR_TXPATH_COEF_12_CHN1_LSB) & BB_RXIQCORR_TXPATH_COEF_12_B1_RXIQCORR_TXPATH_COEF_12_CHN1_MASK)
#define BB_RXIQCORR_TXPATH_COEF_12_B1_RXIQCORR_TXPATH_COEF_12_CHN1_RESET 0
#define BB_RXIQCORR_TXPATH_COEF_12_B1_ADDRESS                        0x0980
#define BB_RXIQCORR_TXPATH_COEF_12_B1_HW_MASK                        0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_12_B1_SW_MASK                        0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_12_B1_HW_WRITE_MASK                  0x00000000
#define BB_RXIQCORR_TXPATH_COEF_12_B1_SW_WRITE_MASK                  0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_12_B1_RSTMASK                        0xffffffff
#define BB_RXIQCORR_TXPATH_COEF_12_B1_RESET                          0x00000000

// 0x0984 (BB_RXIQCORR_TXPATH_COEF_13_B1)
#define BB_RXIQCORR_TXPATH_COEF_13_B1_RXIQCORR_TXPATH_COEF_13_CHN1_MSB 17
#define BB_RXIQCORR_TXPATH_COEF_13_B1_RXIQCORR_TXPATH_COEF_13_CHN1_LSB 0
#define BB_RXIQCORR_TXPATH_COEF_13_B1_RXIQCORR_TXPATH_COEF_13_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_13_B1_RXIQCORR_TXPATH_COEF_13_CHN1_GET(x) (((x) & BB_RXIQCORR_TXPATH_COEF_13_B1_RXIQCORR_TXPATH_COEF_13_CHN1_MASK) >> BB_RXIQCORR_TXPATH_COEF_13_B1_RXIQCORR_TXPATH_COEF_13_CHN1_LSB)
#define BB_RXIQCORR_TXPATH_COEF_13_B1_RXIQCORR_TXPATH_COEF_13_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_TXPATH_COEF_13_B1_RXIQCORR_TXPATH_COEF_13_CHN1_LSB) & BB_RXIQCORR_TXPATH_COEF_13_B1_RXIQCORR_TXPATH_COEF_13_CHN1_MASK)
#define BB_RXIQCORR_TXPATH_COEF_13_B1_RXIQCORR_TXPATH_COEF_13_CHN1_RESET 0
#define BB_RXIQCORR_TXPATH_COEF_13_B1_ADDRESS                        0x0984
#define BB_RXIQCORR_TXPATH_COEF_13_B1_HW_MASK                        0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_13_B1_SW_MASK                        0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_13_B1_HW_WRITE_MASK                  0x00000000
#define BB_RXIQCORR_TXPATH_COEF_13_B1_SW_WRITE_MASK                  0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_13_B1_RSTMASK                        0xffffffff
#define BB_RXIQCORR_TXPATH_COEF_13_B1_RESET                          0x00000000

// 0x0988 (BB_RXIQCORR_TXPATH_COEF_14_B1)
#define BB_RXIQCORR_TXPATH_COEF_14_B1_RXIQCORR_TXPATH_COEF_14_CHN1_MSB 17
#define BB_RXIQCORR_TXPATH_COEF_14_B1_RXIQCORR_TXPATH_COEF_14_CHN1_LSB 0
#define BB_RXIQCORR_TXPATH_COEF_14_B1_RXIQCORR_TXPATH_COEF_14_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_14_B1_RXIQCORR_TXPATH_COEF_14_CHN1_GET(x) (((x) & BB_RXIQCORR_TXPATH_COEF_14_B1_RXIQCORR_TXPATH_COEF_14_CHN1_MASK) >> BB_RXIQCORR_TXPATH_COEF_14_B1_RXIQCORR_TXPATH_COEF_14_CHN1_LSB)
#define BB_RXIQCORR_TXPATH_COEF_14_B1_RXIQCORR_TXPATH_COEF_14_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_TXPATH_COEF_14_B1_RXIQCORR_TXPATH_COEF_14_CHN1_LSB) & BB_RXIQCORR_TXPATH_COEF_14_B1_RXIQCORR_TXPATH_COEF_14_CHN1_MASK)
#define BB_RXIQCORR_TXPATH_COEF_14_B1_RXIQCORR_TXPATH_COEF_14_CHN1_RESET 0
#define BB_RXIQCORR_TXPATH_COEF_14_B1_ADDRESS                        0x0988
#define BB_RXIQCORR_TXPATH_COEF_14_B1_HW_MASK                        0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_14_B1_SW_MASK                        0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_14_B1_HW_WRITE_MASK                  0x00000000
#define BB_RXIQCORR_TXPATH_COEF_14_B1_SW_WRITE_MASK                  0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_14_B1_RSTMASK                        0xffffffff
#define BB_RXIQCORR_TXPATH_COEF_14_B1_RESET                          0x00000000

// 0x098c (BB_RXIQCORR_TXPATH_COEF_15_B1)
#define BB_RXIQCORR_TXPATH_COEF_15_B1_RXIQCORR_TXPATH_COEF_15_CHN1_MSB 17
#define BB_RXIQCORR_TXPATH_COEF_15_B1_RXIQCORR_TXPATH_COEF_15_CHN1_LSB 0
#define BB_RXIQCORR_TXPATH_COEF_15_B1_RXIQCORR_TXPATH_COEF_15_CHN1_MASK 0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_15_B1_RXIQCORR_TXPATH_COEF_15_CHN1_GET(x) (((x) & BB_RXIQCORR_TXPATH_COEF_15_B1_RXIQCORR_TXPATH_COEF_15_CHN1_MASK) >> BB_RXIQCORR_TXPATH_COEF_15_B1_RXIQCORR_TXPATH_COEF_15_CHN1_LSB)
#define BB_RXIQCORR_TXPATH_COEF_15_B1_RXIQCORR_TXPATH_COEF_15_CHN1_SET(x) (((0 | (x)) << BB_RXIQCORR_TXPATH_COEF_15_B1_RXIQCORR_TXPATH_COEF_15_CHN1_LSB) & BB_RXIQCORR_TXPATH_COEF_15_B1_RXIQCORR_TXPATH_COEF_15_CHN1_MASK)
#define BB_RXIQCORR_TXPATH_COEF_15_B1_RXIQCORR_TXPATH_COEF_15_CHN1_RESET 0
#define BB_RXIQCORR_TXPATH_COEF_15_B1_ADDRESS                        0x098c
#define BB_RXIQCORR_TXPATH_COEF_15_B1_HW_MASK                        0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_15_B1_SW_MASK                        0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_15_B1_HW_WRITE_MASK                  0x00000000
#define BB_RXIQCORR_TXPATH_COEF_15_B1_SW_WRITE_MASK                  0x0003ffff
#define BB_RXIQCORR_TXPATH_COEF_15_B1_RSTMASK                        0xffffffff
#define BB_RXIQCORR_TXPATH_COEF_15_B1_RESET                          0x00000000

// 0x0990 (BB_RXCAL_TX_GAIN_TABLE_0_B1)
#define BB_RXCAL_TX_GAIN_TABLE_0_B1_RXCAL_TX_GAIN_TABLE_0_CHN1_MSB   19
#define BB_RXCAL_TX_GAIN_TABLE_0_B1_RXCAL_TX_GAIN_TABLE_0_CHN1_LSB   0
#define BB_RXCAL_TX_GAIN_TABLE_0_B1_RXCAL_TX_GAIN_TABLE_0_CHN1_MASK  0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_0_B1_RXCAL_TX_GAIN_TABLE_0_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_0_B1_RXCAL_TX_GAIN_TABLE_0_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_0_B1_RXCAL_TX_GAIN_TABLE_0_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_0_B1_RXCAL_TX_GAIN_TABLE_0_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_0_B1_RXCAL_TX_GAIN_TABLE_0_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_0_B1_RXCAL_TX_GAIN_TABLE_0_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_0_B1_RXCAL_TX_GAIN_TABLE_0_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_0_B1_ADDRESS                          0x0990
#define BB_RXCAL_TX_GAIN_TABLE_0_B1_HW_MASK                          0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_0_B1_SW_MASK                          0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_0_B1_HW_WRITE_MASK                    0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_0_B1_SW_WRITE_MASK                    0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_0_B1_RSTMASK                          0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_0_B1_RESET                            0x00000000

// 0x0994 (BB_RXCAL_TX_GAIN_TABLE_1_B1)
#define BB_RXCAL_TX_GAIN_TABLE_1_B1_RXCAL_TX_GAIN_TABLE_1_CHN1_MSB   19
#define BB_RXCAL_TX_GAIN_TABLE_1_B1_RXCAL_TX_GAIN_TABLE_1_CHN1_LSB   0
#define BB_RXCAL_TX_GAIN_TABLE_1_B1_RXCAL_TX_GAIN_TABLE_1_CHN1_MASK  0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_1_B1_RXCAL_TX_GAIN_TABLE_1_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_1_B1_RXCAL_TX_GAIN_TABLE_1_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_1_B1_RXCAL_TX_GAIN_TABLE_1_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_1_B1_RXCAL_TX_GAIN_TABLE_1_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_1_B1_RXCAL_TX_GAIN_TABLE_1_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_1_B1_RXCAL_TX_GAIN_TABLE_1_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_1_B1_RXCAL_TX_GAIN_TABLE_1_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_1_B1_ADDRESS                          0x0994
#define BB_RXCAL_TX_GAIN_TABLE_1_B1_HW_MASK                          0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_1_B1_SW_MASK                          0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_1_B1_HW_WRITE_MASK                    0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_1_B1_SW_WRITE_MASK                    0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_1_B1_RSTMASK                          0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_1_B1_RESET                            0x00000000

// 0x0998 (BB_RXCAL_TX_GAIN_TABLE_2_B1)
#define BB_RXCAL_TX_GAIN_TABLE_2_B1_RXCAL_TX_GAIN_TABLE_2_CHN1_MSB   19
#define BB_RXCAL_TX_GAIN_TABLE_2_B1_RXCAL_TX_GAIN_TABLE_2_CHN1_LSB   0
#define BB_RXCAL_TX_GAIN_TABLE_2_B1_RXCAL_TX_GAIN_TABLE_2_CHN1_MASK  0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_2_B1_RXCAL_TX_GAIN_TABLE_2_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_2_B1_RXCAL_TX_GAIN_TABLE_2_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_2_B1_RXCAL_TX_GAIN_TABLE_2_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_2_B1_RXCAL_TX_GAIN_TABLE_2_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_2_B1_RXCAL_TX_GAIN_TABLE_2_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_2_B1_RXCAL_TX_GAIN_TABLE_2_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_2_B1_RXCAL_TX_GAIN_TABLE_2_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_2_B1_ADDRESS                          0x0998
#define BB_RXCAL_TX_GAIN_TABLE_2_B1_HW_MASK                          0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_2_B1_SW_MASK                          0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_2_B1_HW_WRITE_MASK                    0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_2_B1_SW_WRITE_MASK                    0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_2_B1_RSTMASK                          0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_2_B1_RESET                            0x00000000

// 0x099c (BB_RXCAL_TX_GAIN_TABLE_3_B1)
#define BB_RXCAL_TX_GAIN_TABLE_3_B1_RXCAL_TX_GAIN_TABLE_3_CHN1_MSB   19
#define BB_RXCAL_TX_GAIN_TABLE_3_B1_RXCAL_TX_GAIN_TABLE_3_CHN1_LSB   0
#define BB_RXCAL_TX_GAIN_TABLE_3_B1_RXCAL_TX_GAIN_TABLE_3_CHN1_MASK  0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_3_B1_RXCAL_TX_GAIN_TABLE_3_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_3_B1_RXCAL_TX_GAIN_TABLE_3_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_3_B1_RXCAL_TX_GAIN_TABLE_3_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_3_B1_RXCAL_TX_GAIN_TABLE_3_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_3_B1_RXCAL_TX_GAIN_TABLE_3_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_3_B1_RXCAL_TX_GAIN_TABLE_3_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_3_B1_RXCAL_TX_GAIN_TABLE_3_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_3_B1_ADDRESS                          0x099c
#define BB_RXCAL_TX_GAIN_TABLE_3_B1_HW_MASK                          0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_3_B1_SW_MASK                          0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_3_B1_HW_WRITE_MASK                    0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_3_B1_SW_WRITE_MASK                    0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_3_B1_RSTMASK                          0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_3_B1_RESET                            0x00000000

// 0x09a0 (BB_RXCAL_TX_GAIN_TABLE_4_B1)
#define BB_RXCAL_TX_GAIN_TABLE_4_B1_RXCAL_TX_GAIN_TABLE_4_CHN1_MSB   19
#define BB_RXCAL_TX_GAIN_TABLE_4_B1_RXCAL_TX_GAIN_TABLE_4_CHN1_LSB   0
#define BB_RXCAL_TX_GAIN_TABLE_4_B1_RXCAL_TX_GAIN_TABLE_4_CHN1_MASK  0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_4_B1_RXCAL_TX_GAIN_TABLE_4_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_4_B1_RXCAL_TX_GAIN_TABLE_4_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_4_B1_RXCAL_TX_GAIN_TABLE_4_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_4_B1_RXCAL_TX_GAIN_TABLE_4_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_4_B1_RXCAL_TX_GAIN_TABLE_4_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_4_B1_RXCAL_TX_GAIN_TABLE_4_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_4_B1_RXCAL_TX_GAIN_TABLE_4_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_4_B1_ADDRESS                          0x09a0
#define BB_RXCAL_TX_GAIN_TABLE_4_B1_HW_MASK                          0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_4_B1_SW_MASK                          0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_4_B1_HW_WRITE_MASK                    0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_4_B1_SW_WRITE_MASK                    0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_4_B1_RSTMASK                          0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_4_B1_RESET                            0x00000000

// 0x09a4 (BB_RXCAL_TX_GAIN_TABLE_5_B1)
#define BB_RXCAL_TX_GAIN_TABLE_5_B1_RXCAL_TX_GAIN_TABLE_5_CHN1_MSB   19
#define BB_RXCAL_TX_GAIN_TABLE_5_B1_RXCAL_TX_GAIN_TABLE_5_CHN1_LSB   0
#define BB_RXCAL_TX_GAIN_TABLE_5_B1_RXCAL_TX_GAIN_TABLE_5_CHN1_MASK  0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_5_B1_RXCAL_TX_GAIN_TABLE_5_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_5_B1_RXCAL_TX_GAIN_TABLE_5_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_5_B1_RXCAL_TX_GAIN_TABLE_5_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_5_B1_RXCAL_TX_GAIN_TABLE_5_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_5_B1_RXCAL_TX_GAIN_TABLE_5_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_5_B1_RXCAL_TX_GAIN_TABLE_5_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_5_B1_RXCAL_TX_GAIN_TABLE_5_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_5_B1_ADDRESS                          0x09a4
#define BB_RXCAL_TX_GAIN_TABLE_5_B1_HW_MASK                          0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_5_B1_SW_MASK                          0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_5_B1_HW_WRITE_MASK                    0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_5_B1_SW_WRITE_MASK                    0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_5_B1_RSTMASK                          0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_5_B1_RESET                            0x00000000

// 0x09a8 (BB_RXCAL_TX_GAIN_TABLE_6_B1)
#define BB_RXCAL_TX_GAIN_TABLE_6_B1_RXCAL_TX_GAIN_TABLE_6_CHN1_MSB   19
#define BB_RXCAL_TX_GAIN_TABLE_6_B1_RXCAL_TX_GAIN_TABLE_6_CHN1_LSB   0
#define BB_RXCAL_TX_GAIN_TABLE_6_B1_RXCAL_TX_GAIN_TABLE_6_CHN1_MASK  0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_6_B1_RXCAL_TX_GAIN_TABLE_6_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_6_B1_RXCAL_TX_GAIN_TABLE_6_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_6_B1_RXCAL_TX_GAIN_TABLE_6_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_6_B1_RXCAL_TX_GAIN_TABLE_6_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_6_B1_RXCAL_TX_GAIN_TABLE_6_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_6_B1_RXCAL_TX_GAIN_TABLE_6_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_6_B1_RXCAL_TX_GAIN_TABLE_6_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_6_B1_ADDRESS                          0x09a8
#define BB_RXCAL_TX_GAIN_TABLE_6_B1_HW_MASK                          0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_6_B1_SW_MASK                          0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_6_B1_HW_WRITE_MASK                    0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_6_B1_SW_WRITE_MASK                    0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_6_B1_RSTMASK                          0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_6_B1_RESET                            0x00000000

// 0x09ac (BB_RXCAL_TX_GAIN_TABLE_7_B1)
#define BB_RXCAL_TX_GAIN_TABLE_7_B1_RXCAL_TX_GAIN_TABLE_7_CHN1_MSB   19
#define BB_RXCAL_TX_GAIN_TABLE_7_B1_RXCAL_TX_GAIN_TABLE_7_CHN1_LSB   0
#define BB_RXCAL_TX_GAIN_TABLE_7_B1_RXCAL_TX_GAIN_TABLE_7_CHN1_MASK  0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_7_B1_RXCAL_TX_GAIN_TABLE_7_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_7_B1_RXCAL_TX_GAIN_TABLE_7_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_7_B1_RXCAL_TX_GAIN_TABLE_7_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_7_B1_RXCAL_TX_GAIN_TABLE_7_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_7_B1_RXCAL_TX_GAIN_TABLE_7_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_7_B1_RXCAL_TX_GAIN_TABLE_7_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_7_B1_RXCAL_TX_GAIN_TABLE_7_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_7_B1_ADDRESS                          0x09ac
#define BB_RXCAL_TX_GAIN_TABLE_7_B1_HW_MASK                          0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_7_B1_SW_MASK                          0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_7_B1_HW_WRITE_MASK                    0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_7_B1_SW_WRITE_MASK                    0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_7_B1_RSTMASK                          0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_7_B1_RESET                            0x00000000

// 0x09b0 (BB_RXCAL_TX_GAIN_TABLE_8_B1)
#define BB_RXCAL_TX_GAIN_TABLE_8_B1_RXCAL_TX_GAIN_TABLE_8_CHN1_MSB   19
#define BB_RXCAL_TX_GAIN_TABLE_8_B1_RXCAL_TX_GAIN_TABLE_8_CHN1_LSB   0
#define BB_RXCAL_TX_GAIN_TABLE_8_B1_RXCAL_TX_GAIN_TABLE_8_CHN1_MASK  0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_8_B1_RXCAL_TX_GAIN_TABLE_8_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_8_B1_RXCAL_TX_GAIN_TABLE_8_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_8_B1_RXCAL_TX_GAIN_TABLE_8_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_8_B1_RXCAL_TX_GAIN_TABLE_8_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_8_B1_RXCAL_TX_GAIN_TABLE_8_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_8_B1_RXCAL_TX_GAIN_TABLE_8_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_8_B1_RXCAL_TX_GAIN_TABLE_8_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_8_B1_ADDRESS                          0x09b0
#define BB_RXCAL_TX_GAIN_TABLE_8_B1_HW_MASK                          0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_8_B1_SW_MASK                          0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_8_B1_HW_WRITE_MASK                    0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_8_B1_SW_WRITE_MASK                    0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_8_B1_RSTMASK                          0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_8_B1_RESET                            0x00000000

// 0x09b4 (BB_RXCAL_TX_GAIN_TABLE_9_B1)
#define BB_RXCAL_TX_GAIN_TABLE_9_B1_RXCAL_TX_GAIN_TABLE_9_CHN1_MSB   19
#define BB_RXCAL_TX_GAIN_TABLE_9_B1_RXCAL_TX_GAIN_TABLE_9_CHN1_LSB   0
#define BB_RXCAL_TX_GAIN_TABLE_9_B1_RXCAL_TX_GAIN_TABLE_9_CHN1_MASK  0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_9_B1_RXCAL_TX_GAIN_TABLE_9_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_9_B1_RXCAL_TX_GAIN_TABLE_9_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_9_B1_RXCAL_TX_GAIN_TABLE_9_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_9_B1_RXCAL_TX_GAIN_TABLE_9_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_9_B1_RXCAL_TX_GAIN_TABLE_9_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_9_B1_RXCAL_TX_GAIN_TABLE_9_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_9_B1_RXCAL_TX_GAIN_TABLE_9_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_9_B1_ADDRESS                          0x09b4
#define BB_RXCAL_TX_GAIN_TABLE_9_B1_HW_MASK                          0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_9_B1_SW_MASK                          0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_9_B1_HW_WRITE_MASK                    0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_9_B1_SW_WRITE_MASK                    0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_9_B1_RSTMASK                          0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_9_B1_RESET                            0x00000000

// 0x09b8 (BB_RXCAL_TX_GAIN_TABLE_10_B1)
#define BB_RXCAL_TX_GAIN_TABLE_10_B1_RXCAL_TX_GAIN_TABLE_10_CHN1_MSB 19
#define BB_RXCAL_TX_GAIN_TABLE_10_B1_RXCAL_TX_GAIN_TABLE_10_CHN1_LSB 0
#define BB_RXCAL_TX_GAIN_TABLE_10_B1_RXCAL_TX_GAIN_TABLE_10_CHN1_MASK 0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_10_B1_RXCAL_TX_GAIN_TABLE_10_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_10_B1_RXCAL_TX_GAIN_TABLE_10_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_10_B1_RXCAL_TX_GAIN_TABLE_10_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_10_B1_RXCAL_TX_GAIN_TABLE_10_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_10_B1_RXCAL_TX_GAIN_TABLE_10_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_10_B1_RXCAL_TX_GAIN_TABLE_10_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_10_B1_RXCAL_TX_GAIN_TABLE_10_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_10_B1_ADDRESS                         0x09b8
#define BB_RXCAL_TX_GAIN_TABLE_10_B1_HW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_10_B1_SW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_10_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_10_B1_SW_WRITE_MASK                   0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_10_B1_RSTMASK                         0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_10_B1_RESET                           0x00000000

// 0x09bc (BB_RXCAL_TX_GAIN_TABLE_11_B1)
#define BB_RXCAL_TX_GAIN_TABLE_11_B1_RXCAL_TX_GAIN_TABLE_11_CHN1_MSB 19
#define BB_RXCAL_TX_GAIN_TABLE_11_B1_RXCAL_TX_GAIN_TABLE_11_CHN1_LSB 0
#define BB_RXCAL_TX_GAIN_TABLE_11_B1_RXCAL_TX_GAIN_TABLE_11_CHN1_MASK 0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_11_B1_RXCAL_TX_GAIN_TABLE_11_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_11_B1_RXCAL_TX_GAIN_TABLE_11_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_11_B1_RXCAL_TX_GAIN_TABLE_11_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_11_B1_RXCAL_TX_GAIN_TABLE_11_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_11_B1_RXCAL_TX_GAIN_TABLE_11_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_11_B1_RXCAL_TX_GAIN_TABLE_11_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_11_B1_RXCAL_TX_GAIN_TABLE_11_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_11_B1_ADDRESS                         0x09bc
#define BB_RXCAL_TX_GAIN_TABLE_11_B1_HW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_11_B1_SW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_11_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_11_B1_SW_WRITE_MASK                   0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_11_B1_RSTMASK                         0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_11_B1_RESET                           0x00000000

// 0x09c0 (BB_RXCAL_TX_GAIN_TABLE_12_B1)
#define BB_RXCAL_TX_GAIN_TABLE_12_B1_RXCAL_TX_GAIN_TABLE_12_CHN1_MSB 19
#define BB_RXCAL_TX_GAIN_TABLE_12_B1_RXCAL_TX_GAIN_TABLE_12_CHN1_LSB 0
#define BB_RXCAL_TX_GAIN_TABLE_12_B1_RXCAL_TX_GAIN_TABLE_12_CHN1_MASK 0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_12_B1_RXCAL_TX_GAIN_TABLE_12_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_12_B1_RXCAL_TX_GAIN_TABLE_12_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_12_B1_RXCAL_TX_GAIN_TABLE_12_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_12_B1_RXCAL_TX_GAIN_TABLE_12_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_12_B1_RXCAL_TX_GAIN_TABLE_12_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_12_B1_RXCAL_TX_GAIN_TABLE_12_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_12_B1_RXCAL_TX_GAIN_TABLE_12_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_12_B1_ADDRESS                         0x09c0
#define BB_RXCAL_TX_GAIN_TABLE_12_B1_HW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_12_B1_SW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_12_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_12_B1_SW_WRITE_MASK                   0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_12_B1_RSTMASK                         0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_12_B1_RESET                           0x00000000

// 0x09c4 (BB_RXCAL_TX_GAIN_TABLE_13_B1)
#define BB_RXCAL_TX_GAIN_TABLE_13_B1_RXCAL_TX_GAIN_TABLE_13_CHN1_MSB 19
#define BB_RXCAL_TX_GAIN_TABLE_13_B1_RXCAL_TX_GAIN_TABLE_13_CHN1_LSB 0
#define BB_RXCAL_TX_GAIN_TABLE_13_B1_RXCAL_TX_GAIN_TABLE_13_CHN1_MASK 0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_13_B1_RXCAL_TX_GAIN_TABLE_13_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_13_B1_RXCAL_TX_GAIN_TABLE_13_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_13_B1_RXCAL_TX_GAIN_TABLE_13_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_13_B1_RXCAL_TX_GAIN_TABLE_13_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_13_B1_RXCAL_TX_GAIN_TABLE_13_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_13_B1_RXCAL_TX_GAIN_TABLE_13_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_13_B1_RXCAL_TX_GAIN_TABLE_13_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_13_B1_ADDRESS                         0x09c4
#define BB_RXCAL_TX_GAIN_TABLE_13_B1_HW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_13_B1_SW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_13_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_13_B1_SW_WRITE_MASK                   0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_13_B1_RSTMASK                         0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_13_B1_RESET                           0x00000000

// 0x09c8 (BB_RXCAL_TX_GAIN_TABLE_14_B1)
#define BB_RXCAL_TX_GAIN_TABLE_14_B1_RXCAL_TX_GAIN_TABLE_14_CHN1_MSB 19
#define BB_RXCAL_TX_GAIN_TABLE_14_B1_RXCAL_TX_GAIN_TABLE_14_CHN1_LSB 0
#define BB_RXCAL_TX_GAIN_TABLE_14_B1_RXCAL_TX_GAIN_TABLE_14_CHN1_MASK 0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_14_B1_RXCAL_TX_GAIN_TABLE_14_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_14_B1_RXCAL_TX_GAIN_TABLE_14_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_14_B1_RXCAL_TX_GAIN_TABLE_14_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_14_B1_RXCAL_TX_GAIN_TABLE_14_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_14_B1_RXCAL_TX_GAIN_TABLE_14_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_14_B1_RXCAL_TX_GAIN_TABLE_14_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_14_B1_RXCAL_TX_GAIN_TABLE_14_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_14_B1_ADDRESS                         0x09c8
#define BB_RXCAL_TX_GAIN_TABLE_14_B1_HW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_14_B1_SW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_14_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_14_B1_SW_WRITE_MASK                   0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_14_B1_RSTMASK                         0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_14_B1_RESET                           0x00000000

// 0x09cc (BB_RXCAL_TX_GAIN_TABLE_15_B1)
#define BB_RXCAL_TX_GAIN_TABLE_15_B1_RXCAL_TX_GAIN_TABLE_15_CHN1_MSB 19
#define BB_RXCAL_TX_GAIN_TABLE_15_B1_RXCAL_TX_GAIN_TABLE_15_CHN1_LSB 0
#define BB_RXCAL_TX_GAIN_TABLE_15_B1_RXCAL_TX_GAIN_TABLE_15_CHN1_MASK 0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_15_B1_RXCAL_TX_GAIN_TABLE_15_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_15_B1_RXCAL_TX_GAIN_TABLE_15_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_15_B1_RXCAL_TX_GAIN_TABLE_15_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_15_B1_RXCAL_TX_GAIN_TABLE_15_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_15_B1_RXCAL_TX_GAIN_TABLE_15_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_15_B1_RXCAL_TX_GAIN_TABLE_15_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_15_B1_RXCAL_TX_GAIN_TABLE_15_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_15_B1_ADDRESS                         0x09cc
#define BB_RXCAL_TX_GAIN_TABLE_15_B1_HW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_15_B1_SW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_15_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_15_B1_SW_WRITE_MASK                   0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_15_B1_RSTMASK                         0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_15_B1_RESET                           0x00000000

// 0x09d0 (BB_RXCAL_TX_GAIN_TABLE_16_B1)
#define BB_RXCAL_TX_GAIN_TABLE_16_B1_RXCAL_TX_GAIN_TABLE_16_CHN1_MSB 19
#define BB_RXCAL_TX_GAIN_TABLE_16_B1_RXCAL_TX_GAIN_TABLE_16_CHN1_LSB 0
#define BB_RXCAL_TX_GAIN_TABLE_16_B1_RXCAL_TX_GAIN_TABLE_16_CHN1_MASK 0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_16_B1_RXCAL_TX_GAIN_TABLE_16_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_16_B1_RXCAL_TX_GAIN_TABLE_16_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_16_B1_RXCAL_TX_GAIN_TABLE_16_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_16_B1_RXCAL_TX_GAIN_TABLE_16_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_16_B1_RXCAL_TX_GAIN_TABLE_16_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_16_B1_RXCAL_TX_GAIN_TABLE_16_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_16_B1_RXCAL_TX_GAIN_TABLE_16_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_16_B1_ADDRESS                         0x09d0
#define BB_RXCAL_TX_GAIN_TABLE_16_B1_HW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_16_B1_SW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_16_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_16_B1_SW_WRITE_MASK                   0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_16_B1_RSTMASK                         0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_16_B1_RESET                           0x00000000

// 0x09d4 (BB_RXCAL_TX_GAIN_TABLE_17_B1)
#define BB_RXCAL_TX_GAIN_TABLE_17_B1_RXCAL_TX_GAIN_TABLE_17_CHN1_MSB 19
#define BB_RXCAL_TX_GAIN_TABLE_17_B1_RXCAL_TX_GAIN_TABLE_17_CHN1_LSB 0
#define BB_RXCAL_TX_GAIN_TABLE_17_B1_RXCAL_TX_GAIN_TABLE_17_CHN1_MASK 0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_17_B1_RXCAL_TX_GAIN_TABLE_17_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_17_B1_RXCAL_TX_GAIN_TABLE_17_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_17_B1_RXCAL_TX_GAIN_TABLE_17_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_17_B1_RXCAL_TX_GAIN_TABLE_17_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_17_B1_RXCAL_TX_GAIN_TABLE_17_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_17_B1_RXCAL_TX_GAIN_TABLE_17_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_17_B1_RXCAL_TX_GAIN_TABLE_17_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_17_B1_ADDRESS                         0x09d4
#define BB_RXCAL_TX_GAIN_TABLE_17_B1_HW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_17_B1_SW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_17_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_17_B1_SW_WRITE_MASK                   0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_17_B1_RSTMASK                         0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_17_B1_RESET                           0x00000000

// 0x09d8 (BB_RXCAL_TX_GAIN_TABLE_18_B1)
#define BB_RXCAL_TX_GAIN_TABLE_18_B1_RXCAL_TX_GAIN_TABLE_18_CHN1_MSB 19
#define BB_RXCAL_TX_GAIN_TABLE_18_B1_RXCAL_TX_GAIN_TABLE_18_CHN1_LSB 0
#define BB_RXCAL_TX_GAIN_TABLE_18_B1_RXCAL_TX_GAIN_TABLE_18_CHN1_MASK 0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_18_B1_RXCAL_TX_GAIN_TABLE_18_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_18_B1_RXCAL_TX_GAIN_TABLE_18_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_18_B1_RXCAL_TX_GAIN_TABLE_18_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_18_B1_RXCAL_TX_GAIN_TABLE_18_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_18_B1_RXCAL_TX_GAIN_TABLE_18_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_18_B1_RXCAL_TX_GAIN_TABLE_18_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_18_B1_RXCAL_TX_GAIN_TABLE_18_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_18_B1_ADDRESS                         0x09d8
#define BB_RXCAL_TX_GAIN_TABLE_18_B1_HW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_18_B1_SW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_18_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_18_B1_SW_WRITE_MASK                   0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_18_B1_RSTMASK                         0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_18_B1_RESET                           0x00000000

// 0x09dc (BB_RXCAL_TX_GAIN_TABLE_19_B1)
#define BB_RXCAL_TX_GAIN_TABLE_19_B1_RXCAL_TX_GAIN_TABLE_19_CHN1_MSB 19
#define BB_RXCAL_TX_GAIN_TABLE_19_B1_RXCAL_TX_GAIN_TABLE_19_CHN1_LSB 0
#define BB_RXCAL_TX_GAIN_TABLE_19_B1_RXCAL_TX_GAIN_TABLE_19_CHN1_MASK 0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_19_B1_RXCAL_TX_GAIN_TABLE_19_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_19_B1_RXCAL_TX_GAIN_TABLE_19_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_19_B1_RXCAL_TX_GAIN_TABLE_19_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_19_B1_RXCAL_TX_GAIN_TABLE_19_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_19_B1_RXCAL_TX_GAIN_TABLE_19_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_19_B1_RXCAL_TX_GAIN_TABLE_19_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_19_B1_RXCAL_TX_GAIN_TABLE_19_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_19_B1_ADDRESS                         0x09dc
#define BB_RXCAL_TX_GAIN_TABLE_19_B1_HW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_19_B1_SW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_19_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_19_B1_SW_WRITE_MASK                   0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_19_B1_RSTMASK                         0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_19_B1_RESET                           0x00000000

// 0x09e0 (BB_RXCAL_TX_GAIN_TABLE_20_B1)
#define BB_RXCAL_TX_GAIN_TABLE_20_B1_RXCAL_TX_GAIN_TABLE_20_CHN1_MSB 19
#define BB_RXCAL_TX_GAIN_TABLE_20_B1_RXCAL_TX_GAIN_TABLE_20_CHN1_LSB 0
#define BB_RXCAL_TX_GAIN_TABLE_20_B1_RXCAL_TX_GAIN_TABLE_20_CHN1_MASK 0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_20_B1_RXCAL_TX_GAIN_TABLE_20_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_20_B1_RXCAL_TX_GAIN_TABLE_20_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_20_B1_RXCAL_TX_GAIN_TABLE_20_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_20_B1_RXCAL_TX_GAIN_TABLE_20_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_20_B1_RXCAL_TX_GAIN_TABLE_20_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_20_B1_RXCAL_TX_GAIN_TABLE_20_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_20_B1_RXCAL_TX_GAIN_TABLE_20_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_20_B1_ADDRESS                         0x09e0
#define BB_RXCAL_TX_GAIN_TABLE_20_B1_HW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_20_B1_SW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_20_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_20_B1_SW_WRITE_MASK                   0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_20_B1_RSTMASK                         0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_20_B1_RESET                           0x00000000

// 0x09e4 (BB_RXCAL_TX_GAIN_TABLE_21_B1)
#define BB_RXCAL_TX_GAIN_TABLE_21_B1_RXCAL_TX_GAIN_TABLE_21_CHN1_MSB 19
#define BB_RXCAL_TX_GAIN_TABLE_21_B1_RXCAL_TX_GAIN_TABLE_21_CHN1_LSB 0
#define BB_RXCAL_TX_GAIN_TABLE_21_B1_RXCAL_TX_GAIN_TABLE_21_CHN1_MASK 0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_21_B1_RXCAL_TX_GAIN_TABLE_21_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_21_B1_RXCAL_TX_GAIN_TABLE_21_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_21_B1_RXCAL_TX_GAIN_TABLE_21_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_21_B1_RXCAL_TX_GAIN_TABLE_21_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_21_B1_RXCAL_TX_GAIN_TABLE_21_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_21_B1_RXCAL_TX_GAIN_TABLE_21_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_21_B1_RXCAL_TX_GAIN_TABLE_21_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_21_B1_ADDRESS                         0x09e4
#define BB_RXCAL_TX_GAIN_TABLE_21_B1_HW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_21_B1_SW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_21_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_21_B1_SW_WRITE_MASK                   0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_21_B1_RSTMASK                         0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_21_B1_RESET                           0x00000000

// 0x09e8 (BB_RXCAL_TX_GAIN_TABLE_22_B1)
#define BB_RXCAL_TX_GAIN_TABLE_22_B1_RXCAL_TX_GAIN_TABLE_22_CHN1_MSB 19
#define BB_RXCAL_TX_GAIN_TABLE_22_B1_RXCAL_TX_GAIN_TABLE_22_CHN1_LSB 0
#define BB_RXCAL_TX_GAIN_TABLE_22_B1_RXCAL_TX_GAIN_TABLE_22_CHN1_MASK 0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_22_B1_RXCAL_TX_GAIN_TABLE_22_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_22_B1_RXCAL_TX_GAIN_TABLE_22_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_22_B1_RXCAL_TX_GAIN_TABLE_22_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_22_B1_RXCAL_TX_GAIN_TABLE_22_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_22_B1_RXCAL_TX_GAIN_TABLE_22_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_22_B1_RXCAL_TX_GAIN_TABLE_22_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_22_B1_RXCAL_TX_GAIN_TABLE_22_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_22_B1_ADDRESS                         0x09e8
#define BB_RXCAL_TX_GAIN_TABLE_22_B1_HW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_22_B1_SW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_22_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_22_B1_SW_WRITE_MASK                   0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_22_B1_RSTMASK                         0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_22_B1_RESET                           0x00000000

// 0x09ec (BB_RXCAL_TX_GAIN_TABLE_23_B1)
#define BB_RXCAL_TX_GAIN_TABLE_23_B1_RXCAL_TX_GAIN_TABLE_23_CHN1_MSB 19
#define BB_RXCAL_TX_GAIN_TABLE_23_B1_RXCAL_TX_GAIN_TABLE_23_CHN1_LSB 0
#define BB_RXCAL_TX_GAIN_TABLE_23_B1_RXCAL_TX_GAIN_TABLE_23_CHN1_MASK 0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_23_B1_RXCAL_TX_GAIN_TABLE_23_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_23_B1_RXCAL_TX_GAIN_TABLE_23_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_23_B1_RXCAL_TX_GAIN_TABLE_23_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_23_B1_RXCAL_TX_GAIN_TABLE_23_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_23_B1_RXCAL_TX_GAIN_TABLE_23_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_23_B1_RXCAL_TX_GAIN_TABLE_23_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_23_B1_RXCAL_TX_GAIN_TABLE_23_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_23_B1_ADDRESS                         0x09ec
#define BB_RXCAL_TX_GAIN_TABLE_23_B1_HW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_23_B1_SW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_23_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_23_B1_SW_WRITE_MASK                   0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_23_B1_RSTMASK                         0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_23_B1_RESET                           0x00000000

// 0x09f0 (BB_RXCAL_TX_GAIN_TABLE_24_B1)
#define BB_RXCAL_TX_GAIN_TABLE_24_B1_RXCAL_TX_GAIN_TABLE_24_CHN1_MSB 19
#define BB_RXCAL_TX_GAIN_TABLE_24_B1_RXCAL_TX_GAIN_TABLE_24_CHN1_LSB 0
#define BB_RXCAL_TX_GAIN_TABLE_24_B1_RXCAL_TX_GAIN_TABLE_24_CHN1_MASK 0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_24_B1_RXCAL_TX_GAIN_TABLE_24_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_24_B1_RXCAL_TX_GAIN_TABLE_24_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_24_B1_RXCAL_TX_GAIN_TABLE_24_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_24_B1_RXCAL_TX_GAIN_TABLE_24_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_24_B1_RXCAL_TX_GAIN_TABLE_24_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_24_B1_RXCAL_TX_GAIN_TABLE_24_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_24_B1_RXCAL_TX_GAIN_TABLE_24_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_24_B1_ADDRESS                         0x09f0
#define BB_RXCAL_TX_GAIN_TABLE_24_B1_HW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_24_B1_SW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_24_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_24_B1_SW_WRITE_MASK                   0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_24_B1_RSTMASK                         0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_24_B1_RESET                           0x00000000

// 0x09f4 (BB_RXCAL_TX_GAIN_TABLE_25_B1)
#define BB_RXCAL_TX_GAIN_TABLE_25_B1_RXCAL_TX_GAIN_TABLE_25_CHN1_MSB 19
#define BB_RXCAL_TX_GAIN_TABLE_25_B1_RXCAL_TX_GAIN_TABLE_25_CHN1_LSB 0
#define BB_RXCAL_TX_GAIN_TABLE_25_B1_RXCAL_TX_GAIN_TABLE_25_CHN1_MASK 0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_25_B1_RXCAL_TX_GAIN_TABLE_25_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_25_B1_RXCAL_TX_GAIN_TABLE_25_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_25_B1_RXCAL_TX_GAIN_TABLE_25_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_25_B1_RXCAL_TX_GAIN_TABLE_25_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_25_B1_RXCAL_TX_GAIN_TABLE_25_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_25_B1_RXCAL_TX_GAIN_TABLE_25_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_25_B1_RXCAL_TX_GAIN_TABLE_25_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_25_B1_ADDRESS                         0x09f4
#define BB_RXCAL_TX_GAIN_TABLE_25_B1_HW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_25_B1_SW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_25_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_25_B1_SW_WRITE_MASK                   0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_25_B1_RSTMASK                         0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_25_B1_RESET                           0x00000000

// 0x09f8 (BB_RXCAL_TX_GAIN_TABLE_26_B1)
#define BB_RXCAL_TX_GAIN_TABLE_26_B1_RXCAL_TX_GAIN_TABLE_26_CHN1_MSB 19
#define BB_RXCAL_TX_GAIN_TABLE_26_B1_RXCAL_TX_GAIN_TABLE_26_CHN1_LSB 0
#define BB_RXCAL_TX_GAIN_TABLE_26_B1_RXCAL_TX_GAIN_TABLE_26_CHN1_MASK 0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_26_B1_RXCAL_TX_GAIN_TABLE_26_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_26_B1_RXCAL_TX_GAIN_TABLE_26_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_26_B1_RXCAL_TX_GAIN_TABLE_26_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_26_B1_RXCAL_TX_GAIN_TABLE_26_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_26_B1_RXCAL_TX_GAIN_TABLE_26_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_26_B1_RXCAL_TX_GAIN_TABLE_26_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_26_B1_RXCAL_TX_GAIN_TABLE_26_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_26_B1_ADDRESS                         0x09f8
#define BB_RXCAL_TX_GAIN_TABLE_26_B1_HW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_26_B1_SW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_26_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_26_B1_SW_WRITE_MASK                   0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_26_B1_RSTMASK                         0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_26_B1_RESET                           0x00000000

// 0x09fc (BB_RXCAL_TX_GAIN_TABLE_27_B1)
#define BB_RXCAL_TX_GAIN_TABLE_27_B1_RXCAL_TX_GAIN_TABLE_27_CHN1_MSB 19
#define BB_RXCAL_TX_GAIN_TABLE_27_B1_RXCAL_TX_GAIN_TABLE_27_CHN1_LSB 0
#define BB_RXCAL_TX_GAIN_TABLE_27_B1_RXCAL_TX_GAIN_TABLE_27_CHN1_MASK 0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_27_B1_RXCAL_TX_GAIN_TABLE_27_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_27_B1_RXCAL_TX_GAIN_TABLE_27_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_27_B1_RXCAL_TX_GAIN_TABLE_27_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_27_B1_RXCAL_TX_GAIN_TABLE_27_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_27_B1_RXCAL_TX_GAIN_TABLE_27_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_27_B1_RXCAL_TX_GAIN_TABLE_27_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_27_B1_RXCAL_TX_GAIN_TABLE_27_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_27_B1_ADDRESS                         0x09fc
#define BB_RXCAL_TX_GAIN_TABLE_27_B1_HW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_27_B1_SW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_27_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_27_B1_SW_WRITE_MASK                   0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_27_B1_RSTMASK                         0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_27_B1_RESET                           0x00000000

// 0x0a00 (BB_RXCAL_TX_GAIN_TABLE_28_B1)
#define BB_RXCAL_TX_GAIN_TABLE_28_B1_RXCAL_TX_GAIN_TABLE_28_CHN1_MSB 19
#define BB_RXCAL_TX_GAIN_TABLE_28_B1_RXCAL_TX_GAIN_TABLE_28_CHN1_LSB 0
#define BB_RXCAL_TX_GAIN_TABLE_28_B1_RXCAL_TX_GAIN_TABLE_28_CHN1_MASK 0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_28_B1_RXCAL_TX_GAIN_TABLE_28_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_28_B1_RXCAL_TX_GAIN_TABLE_28_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_28_B1_RXCAL_TX_GAIN_TABLE_28_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_28_B1_RXCAL_TX_GAIN_TABLE_28_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_28_B1_RXCAL_TX_GAIN_TABLE_28_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_28_B1_RXCAL_TX_GAIN_TABLE_28_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_28_B1_RXCAL_TX_GAIN_TABLE_28_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_28_B1_ADDRESS                         0x0a00
#define BB_RXCAL_TX_GAIN_TABLE_28_B1_HW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_28_B1_SW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_28_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_28_B1_SW_WRITE_MASK                   0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_28_B1_RSTMASK                         0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_28_B1_RESET                           0x00000000

// 0x0a04 (BB_RXCAL_TX_GAIN_TABLE_29_B1)
#define BB_RXCAL_TX_GAIN_TABLE_29_B1_RXCAL_TX_GAIN_TABLE_29_CHN1_MSB 19
#define BB_RXCAL_TX_GAIN_TABLE_29_B1_RXCAL_TX_GAIN_TABLE_29_CHN1_LSB 0
#define BB_RXCAL_TX_GAIN_TABLE_29_B1_RXCAL_TX_GAIN_TABLE_29_CHN1_MASK 0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_29_B1_RXCAL_TX_GAIN_TABLE_29_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_29_B1_RXCAL_TX_GAIN_TABLE_29_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_29_B1_RXCAL_TX_GAIN_TABLE_29_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_29_B1_RXCAL_TX_GAIN_TABLE_29_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_29_B1_RXCAL_TX_GAIN_TABLE_29_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_29_B1_RXCAL_TX_GAIN_TABLE_29_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_29_B1_RXCAL_TX_GAIN_TABLE_29_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_29_B1_ADDRESS                         0x0a04
#define BB_RXCAL_TX_GAIN_TABLE_29_B1_HW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_29_B1_SW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_29_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_29_B1_SW_WRITE_MASK                   0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_29_B1_RSTMASK                         0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_29_B1_RESET                           0x00000000

// 0x0a08 (BB_RXCAL_TX_GAIN_TABLE_30_B1)
#define BB_RXCAL_TX_GAIN_TABLE_30_B1_RXCAL_TX_GAIN_TABLE_30_CHN1_MSB 19
#define BB_RXCAL_TX_GAIN_TABLE_30_B1_RXCAL_TX_GAIN_TABLE_30_CHN1_LSB 0
#define BB_RXCAL_TX_GAIN_TABLE_30_B1_RXCAL_TX_GAIN_TABLE_30_CHN1_MASK 0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_30_B1_RXCAL_TX_GAIN_TABLE_30_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_30_B1_RXCAL_TX_GAIN_TABLE_30_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_30_B1_RXCAL_TX_GAIN_TABLE_30_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_30_B1_RXCAL_TX_GAIN_TABLE_30_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_30_B1_RXCAL_TX_GAIN_TABLE_30_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_30_B1_RXCAL_TX_GAIN_TABLE_30_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_30_B1_RXCAL_TX_GAIN_TABLE_30_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_30_B1_ADDRESS                         0x0a08
#define BB_RXCAL_TX_GAIN_TABLE_30_B1_HW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_30_B1_SW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_30_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_30_B1_SW_WRITE_MASK                   0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_30_B1_RSTMASK                         0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_30_B1_RESET                           0x00000000

// 0x0a0c (BB_RXCAL_TX_GAIN_TABLE_31_B1)
#define BB_RXCAL_TX_GAIN_TABLE_31_B1_RXCAL_TX_GAIN_TABLE_31_CHN1_MSB 19
#define BB_RXCAL_TX_GAIN_TABLE_31_B1_RXCAL_TX_GAIN_TABLE_31_CHN1_LSB 0
#define BB_RXCAL_TX_GAIN_TABLE_31_B1_RXCAL_TX_GAIN_TABLE_31_CHN1_MASK 0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_31_B1_RXCAL_TX_GAIN_TABLE_31_CHN1_GET(x) (((x) & BB_RXCAL_TX_GAIN_TABLE_31_B1_RXCAL_TX_GAIN_TABLE_31_CHN1_MASK) >> BB_RXCAL_TX_GAIN_TABLE_31_B1_RXCAL_TX_GAIN_TABLE_31_CHN1_LSB)
#define BB_RXCAL_TX_GAIN_TABLE_31_B1_RXCAL_TX_GAIN_TABLE_31_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_GAIN_TABLE_31_B1_RXCAL_TX_GAIN_TABLE_31_CHN1_LSB) & BB_RXCAL_TX_GAIN_TABLE_31_B1_RXCAL_TX_GAIN_TABLE_31_CHN1_MASK)
#define BB_RXCAL_TX_GAIN_TABLE_31_B1_RXCAL_TX_GAIN_TABLE_31_CHN1_RESET 0
#define BB_RXCAL_TX_GAIN_TABLE_31_B1_ADDRESS                         0x0a0c
#define BB_RXCAL_TX_GAIN_TABLE_31_B1_HW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_31_B1_SW_MASK                         0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_31_B1_HW_WRITE_MASK                   0x00000000
#define BB_RXCAL_TX_GAIN_TABLE_31_B1_SW_WRITE_MASK                   0x000fffff
#define BB_RXCAL_TX_GAIN_TABLE_31_B1_RSTMASK                         0xfff00000
#define BB_RXCAL_TX_GAIN_TABLE_31_B1_RESET                           0x00000000

// 0x0a10 (BB_RXCAL_RX_GAIN_TABLE_1_0_B1)
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B1_RXCAL_RX_GAIN_TABLE_1_CHN1_MSB 24
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B1_RXCAL_RX_GAIN_TABLE_1_CHN1_LSB 16
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B1_RXCAL_RX_GAIN_TABLE_1_CHN1_MASK 0x01ff0000
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B1_RXCAL_RX_GAIN_TABLE_1_CHN1_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_1_0_B1_RXCAL_RX_GAIN_TABLE_1_CHN1_MASK) >> BB_RXCAL_RX_GAIN_TABLE_1_0_B1_RXCAL_RX_GAIN_TABLE_1_CHN1_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B1_RXCAL_RX_GAIN_TABLE_1_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_1_0_B1_RXCAL_RX_GAIN_TABLE_1_CHN1_LSB) & BB_RXCAL_RX_GAIN_TABLE_1_0_B1_RXCAL_RX_GAIN_TABLE_1_CHN1_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B1_RXCAL_RX_GAIN_TABLE_1_CHN1_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B1_RXCAL_RX_GAIN_TABLE_0_CHN1_MSB 8
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B1_RXCAL_RX_GAIN_TABLE_0_CHN1_LSB 0
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B1_RXCAL_RX_GAIN_TABLE_0_CHN1_MASK 0x000001ff
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B1_RXCAL_RX_GAIN_TABLE_0_CHN1_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_1_0_B1_RXCAL_RX_GAIN_TABLE_0_CHN1_MASK) >> BB_RXCAL_RX_GAIN_TABLE_1_0_B1_RXCAL_RX_GAIN_TABLE_0_CHN1_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B1_RXCAL_RX_GAIN_TABLE_0_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_1_0_B1_RXCAL_RX_GAIN_TABLE_0_CHN1_LSB) & BB_RXCAL_RX_GAIN_TABLE_1_0_B1_RXCAL_RX_GAIN_TABLE_0_CHN1_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B1_RXCAL_RX_GAIN_TABLE_0_CHN1_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B1_ADDRESS                        0x0a10
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B1_HW_MASK                        0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B1_SW_MASK                        0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B1_HW_WRITE_MASK                  0x00000000
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B1_SW_WRITE_MASK                  0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B1_RSTMASK                        0xfe00fe00
#define BB_RXCAL_RX_GAIN_TABLE_1_0_B1_RESET                          0x00000000

// 0x0a14 (BB_RXCAL_RX_GAIN_TABLE_3_2_B1)
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B1_RXCAL_RX_GAIN_TABLE_3_CHN1_MSB 24
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B1_RXCAL_RX_GAIN_TABLE_3_CHN1_LSB 16
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B1_RXCAL_RX_GAIN_TABLE_3_CHN1_MASK 0x01ff0000
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B1_RXCAL_RX_GAIN_TABLE_3_CHN1_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_3_2_B1_RXCAL_RX_GAIN_TABLE_3_CHN1_MASK) >> BB_RXCAL_RX_GAIN_TABLE_3_2_B1_RXCAL_RX_GAIN_TABLE_3_CHN1_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B1_RXCAL_RX_GAIN_TABLE_3_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_3_2_B1_RXCAL_RX_GAIN_TABLE_3_CHN1_LSB) & BB_RXCAL_RX_GAIN_TABLE_3_2_B1_RXCAL_RX_GAIN_TABLE_3_CHN1_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B1_RXCAL_RX_GAIN_TABLE_3_CHN1_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B1_RXCAL_RX_GAIN_TABLE_2_CHN1_MSB 8
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B1_RXCAL_RX_GAIN_TABLE_2_CHN1_LSB 0
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B1_RXCAL_RX_GAIN_TABLE_2_CHN1_MASK 0x000001ff
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B1_RXCAL_RX_GAIN_TABLE_2_CHN1_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_3_2_B1_RXCAL_RX_GAIN_TABLE_2_CHN1_MASK) >> BB_RXCAL_RX_GAIN_TABLE_3_2_B1_RXCAL_RX_GAIN_TABLE_2_CHN1_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B1_RXCAL_RX_GAIN_TABLE_2_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_3_2_B1_RXCAL_RX_GAIN_TABLE_2_CHN1_LSB) & BB_RXCAL_RX_GAIN_TABLE_3_2_B1_RXCAL_RX_GAIN_TABLE_2_CHN1_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B1_RXCAL_RX_GAIN_TABLE_2_CHN1_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B1_ADDRESS                        0x0a14
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B1_HW_MASK                        0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B1_SW_MASK                        0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B1_HW_WRITE_MASK                  0x00000000
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B1_SW_WRITE_MASK                  0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B1_RSTMASK                        0xfe00fe00
#define BB_RXCAL_RX_GAIN_TABLE_3_2_B1_RESET                          0x00000000

// 0x0a18 (BB_RXCAL_RX_GAIN_TABLE_5_4_B1)
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B1_RXCAL_RX_GAIN_TABLE_5_CHN1_MSB 24
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B1_RXCAL_RX_GAIN_TABLE_5_CHN1_LSB 16
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B1_RXCAL_RX_GAIN_TABLE_5_CHN1_MASK 0x01ff0000
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B1_RXCAL_RX_GAIN_TABLE_5_CHN1_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_5_4_B1_RXCAL_RX_GAIN_TABLE_5_CHN1_MASK) >> BB_RXCAL_RX_GAIN_TABLE_5_4_B1_RXCAL_RX_GAIN_TABLE_5_CHN1_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B1_RXCAL_RX_GAIN_TABLE_5_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_5_4_B1_RXCAL_RX_GAIN_TABLE_5_CHN1_LSB) & BB_RXCAL_RX_GAIN_TABLE_5_4_B1_RXCAL_RX_GAIN_TABLE_5_CHN1_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B1_RXCAL_RX_GAIN_TABLE_5_CHN1_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B1_RXCAL_RX_GAIN_TABLE_4_CHN1_MSB 8
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B1_RXCAL_RX_GAIN_TABLE_4_CHN1_LSB 0
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B1_RXCAL_RX_GAIN_TABLE_4_CHN1_MASK 0x000001ff
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B1_RXCAL_RX_GAIN_TABLE_4_CHN1_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_5_4_B1_RXCAL_RX_GAIN_TABLE_4_CHN1_MASK) >> BB_RXCAL_RX_GAIN_TABLE_5_4_B1_RXCAL_RX_GAIN_TABLE_4_CHN1_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B1_RXCAL_RX_GAIN_TABLE_4_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_5_4_B1_RXCAL_RX_GAIN_TABLE_4_CHN1_LSB) & BB_RXCAL_RX_GAIN_TABLE_5_4_B1_RXCAL_RX_GAIN_TABLE_4_CHN1_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B1_RXCAL_RX_GAIN_TABLE_4_CHN1_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B1_ADDRESS                        0x0a18
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B1_HW_MASK                        0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B1_SW_MASK                        0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B1_HW_WRITE_MASK                  0x00000000
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B1_SW_WRITE_MASK                  0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B1_RSTMASK                        0xfe00fe00
#define BB_RXCAL_RX_GAIN_TABLE_5_4_B1_RESET                          0x00000000

// 0x0a1c (BB_RXCAL_RX_GAIN_TABLE_7_6_B1)
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B1_RXCAL_RX_GAIN_TABLE_7_CHN1_MSB 24
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B1_RXCAL_RX_GAIN_TABLE_7_CHN1_LSB 16
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B1_RXCAL_RX_GAIN_TABLE_7_CHN1_MASK 0x01ff0000
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B1_RXCAL_RX_GAIN_TABLE_7_CHN1_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_7_6_B1_RXCAL_RX_GAIN_TABLE_7_CHN1_MASK) >> BB_RXCAL_RX_GAIN_TABLE_7_6_B1_RXCAL_RX_GAIN_TABLE_7_CHN1_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B1_RXCAL_RX_GAIN_TABLE_7_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_7_6_B1_RXCAL_RX_GAIN_TABLE_7_CHN1_LSB) & BB_RXCAL_RX_GAIN_TABLE_7_6_B1_RXCAL_RX_GAIN_TABLE_7_CHN1_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B1_RXCAL_RX_GAIN_TABLE_7_CHN1_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B1_RXCAL_RX_GAIN_TABLE_6_CHN1_MSB 8
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B1_RXCAL_RX_GAIN_TABLE_6_CHN1_LSB 0
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B1_RXCAL_RX_GAIN_TABLE_6_CHN1_MASK 0x000001ff
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B1_RXCAL_RX_GAIN_TABLE_6_CHN1_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_7_6_B1_RXCAL_RX_GAIN_TABLE_6_CHN1_MASK) >> BB_RXCAL_RX_GAIN_TABLE_7_6_B1_RXCAL_RX_GAIN_TABLE_6_CHN1_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B1_RXCAL_RX_GAIN_TABLE_6_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_7_6_B1_RXCAL_RX_GAIN_TABLE_6_CHN1_LSB) & BB_RXCAL_RX_GAIN_TABLE_7_6_B1_RXCAL_RX_GAIN_TABLE_6_CHN1_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B1_RXCAL_RX_GAIN_TABLE_6_CHN1_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B1_ADDRESS                        0x0a1c
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B1_HW_MASK                        0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B1_SW_MASK                        0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B1_HW_WRITE_MASK                  0x00000000
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B1_SW_WRITE_MASK                  0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B1_RSTMASK                        0xfe00fe00
#define BB_RXCAL_RX_GAIN_TABLE_7_6_B1_RESET                          0x00000000

// 0x0a20 (BB_RXCAL_RX_GAIN_TABLE_9_8_B1)
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B1_RXCAL_RX_GAIN_TABLE_9_CHN1_MSB 24
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B1_RXCAL_RX_GAIN_TABLE_9_CHN1_LSB 16
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B1_RXCAL_RX_GAIN_TABLE_9_CHN1_MASK 0x01ff0000
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B1_RXCAL_RX_GAIN_TABLE_9_CHN1_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_9_8_B1_RXCAL_RX_GAIN_TABLE_9_CHN1_MASK) >> BB_RXCAL_RX_GAIN_TABLE_9_8_B1_RXCAL_RX_GAIN_TABLE_9_CHN1_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B1_RXCAL_RX_GAIN_TABLE_9_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_9_8_B1_RXCAL_RX_GAIN_TABLE_9_CHN1_LSB) & BB_RXCAL_RX_GAIN_TABLE_9_8_B1_RXCAL_RX_GAIN_TABLE_9_CHN1_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B1_RXCAL_RX_GAIN_TABLE_9_CHN1_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B1_RXCAL_RX_GAIN_TABLE_8_CHN1_MSB 8
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B1_RXCAL_RX_GAIN_TABLE_8_CHN1_LSB 0
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B1_RXCAL_RX_GAIN_TABLE_8_CHN1_MASK 0x000001ff
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B1_RXCAL_RX_GAIN_TABLE_8_CHN1_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_9_8_B1_RXCAL_RX_GAIN_TABLE_8_CHN1_MASK) >> BB_RXCAL_RX_GAIN_TABLE_9_8_B1_RXCAL_RX_GAIN_TABLE_8_CHN1_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B1_RXCAL_RX_GAIN_TABLE_8_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_9_8_B1_RXCAL_RX_GAIN_TABLE_8_CHN1_LSB) & BB_RXCAL_RX_GAIN_TABLE_9_8_B1_RXCAL_RX_GAIN_TABLE_8_CHN1_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B1_RXCAL_RX_GAIN_TABLE_8_CHN1_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B1_ADDRESS                        0x0a20
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B1_HW_MASK                        0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B1_SW_MASK                        0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B1_HW_WRITE_MASK                  0x00000000
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B1_SW_WRITE_MASK                  0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B1_RSTMASK                        0xfe00fe00
#define BB_RXCAL_RX_GAIN_TABLE_9_8_B1_RESET                          0x00000000

// 0x0a24 (BB_RXCAL_RX_GAIN_TABLE_11_10_B1)
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B1_RXCAL_RX_GAIN_TABLE_11_CHN1_MSB 24
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B1_RXCAL_RX_GAIN_TABLE_11_CHN1_LSB 16
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B1_RXCAL_RX_GAIN_TABLE_11_CHN1_MASK 0x01ff0000
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B1_RXCAL_RX_GAIN_TABLE_11_CHN1_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_11_10_B1_RXCAL_RX_GAIN_TABLE_11_CHN1_MASK) >> BB_RXCAL_RX_GAIN_TABLE_11_10_B1_RXCAL_RX_GAIN_TABLE_11_CHN1_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B1_RXCAL_RX_GAIN_TABLE_11_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_11_10_B1_RXCAL_RX_GAIN_TABLE_11_CHN1_LSB) & BB_RXCAL_RX_GAIN_TABLE_11_10_B1_RXCAL_RX_GAIN_TABLE_11_CHN1_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B1_RXCAL_RX_GAIN_TABLE_11_CHN1_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B1_RXCAL_RX_GAIN_TABLE_10_CHN1_MSB 8
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B1_RXCAL_RX_GAIN_TABLE_10_CHN1_LSB 0
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B1_RXCAL_RX_GAIN_TABLE_10_CHN1_MASK 0x000001ff
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B1_RXCAL_RX_GAIN_TABLE_10_CHN1_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_11_10_B1_RXCAL_RX_GAIN_TABLE_10_CHN1_MASK) >> BB_RXCAL_RX_GAIN_TABLE_11_10_B1_RXCAL_RX_GAIN_TABLE_10_CHN1_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B1_RXCAL_RX_GAIN_TABLE_10_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_11_10_B1_RXCAL_RX_GAIN_TABLE_10_CHN1_LSB) & BB_RXCAL_RX_GAIN_TABLE_11_10_B1_RXCAL_RX_GAIN_TABLE_10_CHN1_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B1_RXCAL_RX_GAIN_TABLE_10_CHN1_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B1_ADDRESS                      0x0a24
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B1_HW_MASK                      0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B1_SW_MASK                      0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B1_HW_WRITE_MASK                0x00000000
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B1_SW_WRITE_MASK                0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B1_RSTMASK                      0xfe00fe00
#define BB_RXCAL_RX_GAIN_TABLE_11_10_B1_RESET                        0x00000000

// 0x0a28 (BB_RXCAL_RX_GAIN_TABLE_13_12_B1)
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B1_RXCAL_RX_GAIN_TABLE_13_CHN1_MSB 24
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B1_RXCAL_RX_GAIN_TABLE_13_CHN1_LSB 16
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B1_RXCAL_RX_GAIN_TABLE_13_CHN1_MASK 0x01ff0000
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B1_RXCAL_RX_GAIN_TABLE_13_CHN1_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_13_12_B1_RXCAL_RX_GAIN_TABLE_13_CHN1_MASK) >> BB_RXCAL_RX_GAIN_TABLE_13_12_B1_RXCAL_RX_GAIN_TABLE_13_CHN1_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B1_RXCAL_RX_GAIN_TABLE_13_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_13_12_B1_RXCAL_RX_GAIN_TABLE_13_CHN1_LSB) & BB_RXCAL_RX_GAIN_TABLE_13_12_B1_RXCAL_RX_GAIN_TABLE_13_CHN1_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B1_RXCAL_RX_GAIN_TABLE_13_CHN1_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B1_RXCAL_RX_GAIN_TABLE_12_CHN1_MSB 8
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B1_RXCAL_RX_GAIN_TABLE_12_CHN1_LSB 0
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B1_RXCAL_RX_GAIN_TABLE_12_CHN1_MASK 0x000001ff
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B1_RXCAL_RX_GAIN_TABLE_12_CHN1_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_13_12_B1_RXCAL_RX_GAIN_TABLE_12_CHN1_MASK) >> BB_RXCAL_RX_GAIN_TABLE_13_12_B1_RXCAL_RX_GAIN_TABLE_12_CHN1_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B1_RXCAL_RX_GAIN_TABLE_12_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_13_12_B1_RXCAL_RX_GAIN_TABLE_12_CHN1_LSB) & BB_RXCAL_RX_GAIN_TABLE_13_12_B1_RXCAL_RX_GAIN_TABLE_12_CHN1_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B1_RXCAL_RX_GAIN_TABLE_12_CHN1_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B1_ADDRESS                      0x0a28
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B1_HW_MASK                      0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B1_SW_MASK                      0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B1_HW_WRITE_MASK                0x00000000
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B1_SW_WRITE_MASK                0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B1_RSTMASK                      0xfe00fe00
#define BB_RXCAL_RX_GAIN_TABLE_13_12_B1_RESET                        0x00000000

// 0x0a2c (BB_RXCAL_RX_GAIN_TABLE_15_14_B1)
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B1_RXCAL_RX_GAIN_TABLE_15_CHN1_MSB 24
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B1_RXCAL_RX_GAIN_TABLE_15_CHN1_LSB 16
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B1_RXCAL_RX_GAIN_TABLE_15_CHN1_MASK 0x01ff0000
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B1_RXCAL_RX_GAIN_TABLE_15_CHN1_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_15_14_B1_RXCAL_RX_GAIN_TABLE_15_CHN1_MASK) >> BB_RXCAL_RX_GAIN_TABLE_15_14_B1_RXCAL_RX_GAIN_TABLE_15_CHN1_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B1_RXCAL_RX_GAIN_TABLE_15_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_15_14_B1_RXCAL_RX_GAIN_TABLE_15_CHN1_LSB) & BB_RXCAL_RX_GAIN_TABLE_15_14_B1_RXCAL_RX_GAIN_TABLE_15_CHN1_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B1_RXCAL_RX_GAIN_TABLE_15_CHN1_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B1_RXCAL_RX_GAIN_TABLE_14_CHN1_MSB 8
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B1_RXCAL_RX_GAIN_TABLE_14_CHN1_LSB 0
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B1_RXCAL_RX_GAIN_TABLE_14_CHN1_MASK 0x000001ff
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B1_RXCAL_RX_GAIN_TABLE_14_CHN1_GET(x) (((x) & BB_RXCAL_RX_GAIN_TABLE_15_14_B1_RXCAL_RX_GAIN_TABLE_14_CHN1_MASK) >> BB_RXCAL_RX_GAIN_TABLE_15_14_B1_RXCAL_RX_GAIN_TABLE_14_CHN1_LSB)
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B1_RXCAL_RX_GAIN_TABLE_14_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_RX_GAIN_TABLE_15_14_B1_RXCAL_RX_GAIN_TABLE_14_CHN1_LSB) & BB_RXCAL_RX_GAIN_TABLE_15_14_B1_RXCAL_RX_GAIN_TABLE_14_CHN1_MASK)
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B1_RXCAL_RX_GAIN_TABLE_14_CHN1_RESET 0
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B1_ADDRESS                      0x0a2c
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B1_HW_MASK                      0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B1_SW_MASK                      0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B1_HW_WRITE_MASK                0x00000000
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B1_SW_WRITE_MASK                0x01ff01ff
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B1_RSTMASK                      0xfe00fe00
#define BB_RXCAL_RX_GAIN_TABLE_15_14_B1_RESET                        0x00000000

// 0x0a30 (BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_3_CHN1_MSB 29
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_3_CHN1_LSB 24
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_3_CHN1_MASK 0x3f000000
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_3_CHN1_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_3_CHN1_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_3_CHN1_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_3_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_3_CHN1_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_3_CHN1_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_3_CHN1_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_2_CHN1_MSB 21
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_2_CHN1_LSB 16
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_2_CHN1_MASK 0x003f0000
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_2_CHN1_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_2_CHN1_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_2_CHN1_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_2_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_2_CHN1_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_2_CHN1_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_2_CHN1_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_1_CHN1_MSB 13
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_1_CHN1_LSB 8
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_1_CHN1_MASK 0x00003f00
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_1_CHN1_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_1_CHN1_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_1_CHN1_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_1_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_1_CHN1_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_1_CHN1_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_1_CHN1_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_0_CHN1_MSB 5
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_0_CHN1_LSB 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_0_CHN1_MASK 0x0000003f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_0_CHN1_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_0_CHN1_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_0_CHN1_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_0_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_0_CHN1_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_0_CHN1_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RXCAL_GAIN_DELTA_DB_TABLE_0_CHN1_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_ADDRESS                  0x0a30
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_HW_MASK                  0x3f3f3f3f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_SW_MASK                  0x3f3f3f3f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_HW_WRITE_MASK            0x00000000
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_SW_WRITE_MASK            0x3f3f3f3f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RSTMASK                  0xc0c0c0c0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_3_0_B1_RESET                    0x00000000

// 0x0a34 (BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_7_CHN1_MSB 29
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_7_CHN1_LSB 24
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_7_CHN1_MASK 0x3f000000
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_7_CHN1_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_7_CHN1_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_7_CHN1_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_7_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_7_CHN1_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_7_CHN1_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_7_CHN1_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_6_CHN1_MSB 21
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_6_CHN1_LSB 16
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_6_CHN1_MASK 0x003f0000
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_6_CHN1_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_6_CHN1_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_6_CHN1_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_6_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_6_CHN1_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_6_CHN1_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_6_CHN1_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_5_CHN1_MSB 13
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_5_CHN1_LSB 8
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_5_CHN1_MASK 0x00003f00
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_5_CHN1_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_5_CHN1_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_5_CHN1_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_5_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_5_CHN1_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_5_CHN1_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_5_CHN1_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_4_CHN1_MSB 5
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_4_CHN1_LSB 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_4_CHN1_MASK 0x0000003f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_4_CHN1_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_4_CHN1_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_4_CHN1_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_4_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_4_CHN1_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_4_CHN1_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RXCAL_GAIN_DELTA_DB_TABLE_4_CHN1_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_ADDRESS                  0x0a34
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_HW_MASK                  0x3f3f3f3f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_SW_MASK                  0x3f3f3f3f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_HW_WRITE_MASK            0x00000000
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_SW_WRITE_MASK            0x3f3f3f3f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RSTMASK                  0xc0c0c0c0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_7_4_B1_RESET                    0x00000000

// 0x0a38 (BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_11_CHN1_MSB 29
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_11_CHN1_LSB 24
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_11_CHN1_MASK 0x3f000000
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_11_CHN1_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_11_CHN1_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_11_CHN1_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_11_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_11_CHN1_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_11_CHN1_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_11_CHN1_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_10_CHN1_MSB 21
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_10_CHN1_LSB 16
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_10_CHN1_MASK 0x003f0000
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_10_CHN1_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_10_CHN1_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_10_CHN1_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_10_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_10_CHN1_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_10_CHN1_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_10_CHN1_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_9_CHN1_MSB 13
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_9_CHN1_LSB 8
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_9_CHN1_MASK 0x00003f00
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_9_CHN1_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_9_CHN1_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_9_CHN1_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_9_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_9_CHN1_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_9_CHN1_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_9_CHN1_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_8_CHN1_MSB 5
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_8_CHN1_LSB 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_8_CHN1_MASK 0x0000003f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_8_CHN1_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_8_CHN1_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_8_CHN1_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_8_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_8_CHN1_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_8_CHN1_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RXCAL_GAIN_DELTA_DB_TABLE_8_CHN1_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_ADDRESS                 0x0a38
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_HW_MASK                 0x3f3f3f3f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_SW_MASK                 0x3f3f3f3f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_HW_WRITE_MASK           0x00000000
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_SW_WRITE_MASK           0x3f3f3f3f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RSTMASK                 0xc0c0c0c0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_11_8_B1_RESET                   0x00000000

// 0x0a3c (BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_15_CHN1_MSB 29
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_15_CHN1_LSB 24
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_15_CHN1_MASK 0x3f000000
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_15_CHN1_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_15_CHN1_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_15_CHN1_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_15_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_15_CHN1_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_15_CHN1_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_15_CHN1_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_14_CHN1_MSB 21
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_14_CHN1_LSB 16
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_14_CHN1_MASK 0x003f0000
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_14_CHN1_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_14_CHN1_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_14_CHN1_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_14_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_14_CHN1_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_14_CHN1_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_14_CHN1_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_13_CHN1_MSB 13
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_13_CHN1_LSB 8
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_13_CHN1_MASK 0x00003f00
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_13_CHN1_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_13_CHN1_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_13_CHN1_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_13_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_13_CHN1_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_13_CHN1_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_13_CHN1_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_12_CHN1_MSB 5
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_12_CHN1_LSB 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_12_CHN1_MASK 0x0000003f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_12_CHN1_GET(x) (((x) & BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_12_CHN1_MASK) >> BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_12_CHN1_LSB)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_12_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_12_CHN1_LSB) & BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_12_CHN1_MASK)
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RXCAL_GAIN_DELTA_DB_TABLE_12_CHN1_RESET 0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_ADDRESS                0x0a3c
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_HW_MASK                0x3f3f3f3f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_SW_MASK                0x3f3f3f3f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_HW_WRITE_MASK          0x00000000
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_SW_WRITE_MASK          0x3f3f3f3f
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RSTMASK                0xc0c0c0c0
#define BB_RXCAL_GAIN_DELTA_DB_TABLE_15_12_B1_RESET                  0x00000000

// 0x0a40 (BB_RXCAL_TX_IQCORR_IDX_7_0_B1)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_7_CHN1_MSB 31
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_7_CHN1_LSB 28
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_7_CHN1_MASK 0xf0000000
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_7_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_7_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_7_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_7_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_7_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_7_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_7_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_6_CHN1_MSB 27
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_6_CHN1_LSB 24
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_6_CHN1_MASK 0x0f000000
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_6_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_6_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_6_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_6_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_6_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_6_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_6_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_5_CHN1_MSB 23
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_5_CHN1_LSB 20
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_5_CHN1_MASK 0x00f00000
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_5_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_5_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_5_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_5_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_5_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_5_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_5_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_4_CHN1_MSB 19
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_4_CHN1_LSB 16
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_4_CHN1_MASK 0x000f0000
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_4_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_4_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_4_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_4_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_4_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_4_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_4_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_3_CHN1_MSB 15
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_3_CHN1_LSB 12
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_3_CHN1_MASK 0x0000f000
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_3_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_3_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_3_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_3_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_3_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_3_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_3_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_2_CHN1_MSB 11
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_2_CHN1_LSB 8
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_2_CHN1_MASK 0x00000f00
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_2_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_2_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_2_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_2_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_2_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_2_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_2_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_1_CHN1_MSB 7
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_1_CHN1_LSB 4
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_1_CHN1_MASK 0x000000f0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_1_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_1_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_1_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_1_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_1_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_1_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_1_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_0_CHN1_MSB 3
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_0_CHN1_LSB 0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_0_CHN1_MASK 0x0000000f
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_0_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_0_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_0_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_0_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_0_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_0_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RXCAL_TX_IQCORR_IDX_0_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_ADDRESS                        0x0a40
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_HW_MASK                        0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_SW_MASK                        0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_HW_WRITE_MASK                  0x00000000
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_SW_WRITE_MASK                  0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RSTMASK                        0x00000000
#define BB_RXCAL_TX_IQCORR_IDX_7_0_B1_RESET                          0x00000000

// 0x0a44 (BB_RXCAL_TX_IQCORR_IDX_15_8_B1)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_15_CHN1_MSB 31
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_15_CHN1_LSB 28
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_15_CHN1_MASK 0xf0000000
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_15_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_15_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_15_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_15_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_15_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_15_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_15_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_14_CHN1_MSB 27
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_14_CHN1_LSB 24
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_14_CHN1_MASK 0x0f000000
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_14_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_14_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_14_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_14_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_14_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_14_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_14_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_13_CHN1_MSB 23
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_13_CHN1_LSB 20
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_13_CHN1_MASK 0x00f00000
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_13_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_13_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_13_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_13_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_13_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_13_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_13_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_12_CHN1_MSB 19
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_12_CHN1_LSB 16
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_12_CHN1_MASK 0x000f0000
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_12_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_12_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_12_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_12_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_12_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_12_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_12_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_11_CHN1_MSB 15
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_11_CHN1_LSB 12
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_11_CHN1_MASK 0x0000f000
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_11_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_11_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_11_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_11_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_11_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_11_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_11_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_10_CHN1_MSB 11
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_10_CHN1_LSB 8
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_10_CHN1_MASK 0x00000f00
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_10_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_10_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_10_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_10_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_10_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_10_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_10_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_9_CHN1_MSB 7
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_9_CHN1_LSB 4
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_9_CHN1_MASK 0x000000f0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_9_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_9_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_9_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_9_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_9_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_9_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_9_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_8_CHN1_MSB 3
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_8_CHN1_LSB 0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_8_CHN1_MASK 0x0000000f
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_8_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_8_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_8_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_8_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_8_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_8_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RXCAL_TX_IQCORR_IDX_8_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_ADDRESS                       0x0a44
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_HW_MASK                       0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_SW_MASK                       0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_HW_WRITE_MASK                 0x00000000
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_SW_WRITE_MASK                 0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RSTMASK                       0x00000000
#define BB_RXCAL_TX_IQCORR_IDX_15_8_B1_RESET                         0x00000000

// 0x0a48 (BB_RXCAL_TX_IQCORR_IDX_23_16_B1)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_23_CHN1_MSB 31
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_23_CHN1_LSB 28
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_23_CHN1_MASK 0xf0000000
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_23_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_23_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_23_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_23_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_23_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_23_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_23_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_22_CHN1_MSB 27
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_22_CHN1_LSB 24
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_22_CHN1_MASK 0x0f000000
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_22_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_22_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_22_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_22_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_22_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_22_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_22_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_21_CHN1_MSB 23
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_21_CHN1_LSB 20
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_21_CHN1_MASK 0x00f00000
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_21_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_21_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_21_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_21_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_21_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_21_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_21_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_20_CHN1_MSB 19
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_20_CHN1_LSB 16
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_20_CHN1_MASK 0x000f0000
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_20_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_20_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_20_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_20_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_20_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_20_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_20_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_19_CHN1_MSB 15
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_19_CHN1_LSB 12
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_19_CHN1_MASK 0x0000f000
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_19_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_19_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_19_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_19_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_19_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_19_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_19_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_18_CHN1_MSB 11
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_18_CHN1_LSB 8
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_18_CHN1_MASK 0x00000f00
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_18_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_18_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_18_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_18_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_18_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_18_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_18_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_17_CHN1_MSB 7
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_17_CHN1_LSB 4
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_17_CHN1_MASK 0x000000f0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_17_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_17_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_17_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_17_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_17_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_17_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_17_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_16_CHN1_MSB 3
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_16_CHN1_LSB 0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_16_CHN1_MASK 0x0000000f
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_16_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_16_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_16_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_16_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_16_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_16_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RXCAL_TX_IQCORR_IDX_16_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_ADDRESS                      0x0a48
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_HW_MASK                      0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_SW_MASK                      0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_HW_WRITE_MASK                0x00000000
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_SW_WRITE_MASK                0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RSTMASK                      0x00000000
#define BB_RXCAL_TX_IQCORR_IDX_23_16_B1_RESET                        0x00000000

// 0x0a4c (BB_RXCAL_TX_IQCORR_IDX_31_24_B1)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_31_CHN1_MSB 31
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_31_CHN1_LSB 28
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_31_CHN1_MASK 0xf0000000
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_31_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_31_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_31_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_31_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_31_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_31_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_31_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_30_CHN1_MSB 27
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_30_CHN1_LSB 24
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_30_CHN1_MASK 0x0f000000
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_30_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_30_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_30_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_30_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_30_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_30_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_30_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_29_CHN1_MSB 23
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_29_CHN1_LSB 20
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_29_CHN1_MASK 0x00f00000
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_29_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_29_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_29_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_29_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_29_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_29_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_29_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_28_CHN1_MSB 19
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_28_CHN1_LSB 16
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_28_CHN1_MASK 0x000f0000
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_28_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_28_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_28_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_28_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_28_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_28_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_28_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_27_CHN1_MSB 15
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_27_CHN1_LSB 12
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_27_CHN1_MASK 0x0000f000
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_27_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_27_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_27_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_27_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_27_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_27_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_27_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_26_CHN1_MSB 11
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_26_CHN1_LSB 8
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_26_CHN1_MASK 0x00000f00
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_26_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_26_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_26_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_26_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_26_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_26_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_26_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_25_CHN1_MSB 7
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_25_CHN1_LSB 4
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_25_CHN1_MASK 0x000000f0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_25_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_25_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_25_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_25_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_25_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_25_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_25_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_24_CHN1_MSB 3
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_24_CHN1_LSB 0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_24_CHN1_MASK 0x0000000f
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_24_CHN1_GET(x) (((x) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_24_CHN1_MASK) >> BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_24_CHN1_LSB)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_24_CHN1_SET(x) (((0 | (x)) << BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_24_CHN1_LSB) & BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_24_CHN1_MASK)
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RXCAL_TX_IQCORR_IDX_24_CHN1_RESET 0
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_ADDRESS                      0x0a4c
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_HW_MASK                      0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_SW_MASK                      0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_HW_WRITE_MASK                0x00000000
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_SW_WRITE_MASK                0xffffffff
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RSTMASK                      0x00000000
#define BB_RXCAL_TX_IQCORR_IDX_31_24_B1_RESET                        0x00000000

// 0x0b00 (BB_CHANINFO_VHT80_B1_0)
#define BB_CHANINFO_VHT80_B1_0_CHANINFO_VHT80_CHN1_MSB               31
#define BB_CHANINFO_VHT80_B1_0_CHANINFO_VHT80_CHN1_LSB               0
#define BB_CHANINFO_VHT80_B1_0_CHANINFO_VHT80_CHN1_MASK              0xffffffff
#define BB_CHANINFO_VHT80_B1_0_CHANINFO_VHT80_CHN1_GET(x)            (((x) & BB_CHANINFO_VHT80_B1_0_CHANINFO_VHT80_CHN1_MASK) >> BB_CHANINFO_VHT80_B1_0_CHANINFO_VHT80_CHN1_LSB)
#define BB_CHANINFO_VHT80_B1_0_CHANINFO_VHT80_CHN1_SET(x)            (((0 | (x)) << BB_CHANINFO_VHT80_B1_0_CHANINFO_VHT80_CHN1_LSB) & BB_CHANINFO_VHT80_B1_0_CHANINFO_VHT80_CHN1_MASK)
#define BB_CHANINFO_VHT80_B1_0_CHANINFO_VHT80_CHN1_RESET             0
#define BB_CHANINFO_VHT80_B1_0_ADDRESS                               0x0b00
#define BB_CHANINFO_VHT80_B1_ADDRESS                                 BB_CHANINFO_VHT80_B1_0_ADDRESS
#define BB_CHANINFO_VHT80_B1_0_HW_MASK                               0xffffffff
#define BB_CHANINFO_VHT80_B1_0_SW_MASK                               0xffffffff
#define BB_CHANINFO_VHT80_B1_0_HW_WRITE_MASK                         0xffffffff
#define BB_CHANINFO_VHT80_B1_0_SW_WRITE_MASK                         0x00000000
#define BB_CHANINFO_VHT80_B1_0_RSTMASK                               0x00000000
#define BB_CHANINFO_VHT80_B1_0_RESET                                 0x00000000

// Skip b04 (BB_CHANINFO_VHT80_B1_1) - bfc (BB_CHANINFO_VHT80_B1_63) for brevity
// 0x8aac (BB_CHN1_TABLES_DUMMY_1)
#define BB_CHN1_TABLES_DUMMY_1_DUMMY1_MSB                            31
#define BB_CHN1_TABLES_DUMMY_1_DUMMY1_LSB                            0
#define BB_CHN1_TABLES_DUMMY_1_DUMMY1_MASK                           0xffffffff
#define BB_CHN1_TABLES_DUMMY_1_DUMMY1_GET(x)                         (((x) & BB_CHN1_TABLES_DUMMY_1_DUMMY1_MASK) >> BB_CHN1_TABLES_DUMMY_1_DUMMY1_LSB)
#define BB_CHN1_TABLES_DUMMY_1_DUMMY1_SET(x)                         (((0 | (x)) << BB_CHN1_TABLES_DUMMY_1_DUMMY1_LSB) & BB_CHN1_TABLES_DUMMY_1_DUMMY1_MASK)
#define BB_CHN1_TABLES_DUMMY_1_DUMMY1_RESET                          0
#define BB_CHN1_TABLES_DUMMY_1_ADDRESS                               0x8aac
#define BB_CHN1_TABLES_DUMMY_1_HW_MASK                               0xffffffff
#define BB_CHN1_TABLES_DUMMY_1_SW_MASK                               0xffffffff
#define BB_CHN1_TABLES_DUMMY_1_HW_WRITE_MASK                         0x00000000
#define BB_CHN1_TABLES_DUMMY_1_SW_WRITE_MASK                         0xffffffff
#define BB_CHN1_TABLES_DUMMY_1_RSTMASK                               0x00000000
#define BB_CHN1_TABLES_DUMMY_1_RESET                                 0x00000000


#endif /* _CHN1_TABLE_MAP_H_ */
